A semiconductor device is provided. The semiconductor device includes an electric field (E-field) suppression layer formed over a termination region. The E-field suppression layer is patterned with openings over metal contact areas. The E-field suppression layer has a thickness such that an electric field strength above the E-field suppression layer is below a dielectric strength of an adjacent material when the semiconductor device is operating at or below a maximum voltage.

Provided are a diode and a manufacturing method therefor. The diode includes: a nitride channel layer; a nitride barrier layer, formed on the nitride channel layer; an oxidation forming layer, wherein a part of the oxidation forming layer is positioned in the nitride barrier layer, and a surface of the oxidation forming layer away from the nitride channel layer is flush with a surface of the nitride barrier layer away from the nitride channel layer; a passivation layer, formed on the nitride barrier layer, wherein the passivation layer includes a first groove penetrating through the passivation layer to expose the oxidation forming layer and a part of the nitride barrier layer; and a first electrode, formed in the first groove, wherein the first electrode is in contact with the nitride barrier layer and the oxidation forming layer.

A method for manufacturing a semiconductor device includes forming semiconductor devices from a semiconductor wafer and identifying a position of the semiconductor device in the semiconductor wafer, wherein the forming the semiconductor devices includes forming a first repeating pattern including i semiconductor devices each having a unique pattern, forming a second repeating pattern including j semiconductor devices each having a unique pattern, defining semiconductor devices on the semiconductor wafer such that each of the k semiconductor devices has a unique pattern based on the first and second repeating patterns, and grinding a backside of the semiconductor wafer, wherein each unique pattern of the k semiconductor devices is composed of a combination of the unique patterns of the first and second repeating patterns, wherein the position of the semiconductor device is identified based on the unique patterns of the first and second repeating patterns and an angle of a grinding mark.

A field-effect transistor includes a gate electrode formed on an electron supply layer thereon, a source electrode and a drain electrode thereon; and also the field-effect transistor includes an insulation film for covering the electron supply layer, and an opening portion of the insulation film, having trapezoidal prism's oblique contour faces, being provided in a region to form the gate electrode in the insulation film. It is so arranged that the gate electrode is made to have a Schottky junction with respect to a region where the electron supply layer is exposed through the opening portion, and also that the trapezoidal prism's oblique contour faces each formed by the opening portion have inclination angles in a range from 25 degrees to 75 degrees with respect to a surface of the electron supply layer.

The invention discloses a display panel, comprising: a first substrate including a display region and a peripheral region adjacent to each other; a plurality of pixel units disposed on the first substrate and located in the display region; a planarization layer disposed on the first substrate and located in the display region and the peripheral region; and an organic passivation layer disposed on the first substrate, covering the planarization layer and located in the display region and the peripheral region; wherein the planarization layer further comprises a first region planarization layer located in the display region, and a second region planarization layer located in the peripheral region, the first region planarization layer is formed with a first sidewall in a boundary region between the display region and the peripheral region, and a height of the first sidewall is greater than a height of the first region planarization layer. The invention can effectively reduce probability of the organic passivation layer on sidewalls of the passivation layers, and can better avoid moisture from penetrating the organic material into the display panel.

A method includes placing an electronic die and a photonic die over a carrier, with a back surface of the electronic die and a front surface of the photonic die facing the carrier. The method further includes encapsulating the electronic die and the photonic die in an encapsulant, planarizing the encapsulant until an electrical connector of the electronic die and a conductive feature of the photonic die are revealed, and forming redistribution lines over the encapsulant. The redistribution lines electrically connect the electronic die to the photonic die. An optical coupler is attached to the photonic die. An optical fiber attached to the optical coupler is configured to optically couple to the photonic die.

An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate and a first chip pad on a first bottom surface of the first semiconductor substrate, a second semiconductor chip including a second semiconductor substrate and a second chip pad on a second top surface of the second semiconductor substrate, a lower redistribution structure provided under the first semiconductor chip and the second semiconductor chip, the lower redistribution structure including a lower redistribution pattern, the lower redistribution pattern including a first lower redistribution via pattern contacting the first chip pad, a molding layer covering the first semiconductor chip and the second semiconductor chip, an upper redistribution structure including an upper redistribution pattern, the upper redistribution pattern including a first upper redistribution via pattern connected to the second chip pad, and a conductive connection structure electrically connecting the lower redistribution pattern to the upper redistribution pattern.

A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.