Apparatuses and methods for manufacturing chips are described. An example method includes: forming at least one first dielectric layer above a substrate; forming at least one second dielectric layer above the first dielectric layer; forming a cover layer above the at least one second dielectric layer; forming a groove above the substrate by etching; covering at least an edge surface of the at least one first dielectric layer in the groove with a liner including polymer; forming a hole through the cover layer and a portion of the at least one second dielectric layer; depositing a conductive layer in the hole, on the cover layer and the liner; and forming a conductive pillar on the conductive layer in the hole by electroplating.

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

A semiconductor assembly includes a laminate substrate that includes a plurality of laminate layers of electrically insulating material stacked on top of one another, a semiconductor package that includes a package body of electrically insulating encapsulant material and a plurality of electrical contacts that are exposed from the package body, wherein the semiconductor package is embedded within the laminate layers of the laminate substrate, wherein the semiconductor package comprises a delamination mitigation feature, wherein the delamination mitigation feature comprises one or both of a macrostructure that engages with the laminate layers, and a roughened surface of microstructures that enhances adhesion between the semiconductor package and the laminate layers.

The semiconductor device includes a mesa diode structure(20) and a protective layer(17b). The mesa diode structure includes, from bottom to top, a P-type semiconductor layer(11), a first N-type semiconductor layer(12), and a second N-type semiconductor layer(13) having a higher impurity concentration than the first N-type semiconductor layer. The protective layer is arranged on a side wall around the mesa diode structure seen in a plane. Specifically, the protective layer is arranged on an upper side surface(11c) of the P-type semiconductor layer and on side surfaces(12a,13a) of the first N-type semiconductor layer and the second N-type semiconductor layer, but is not arranged on a lower side surface of the P-type semiconductor layer. A bevel angle(30) of a PN junction plane between the P-type semiconductor layer and the first N-type semiconductor layer to the upper side surface of the P-type semiconductor layer is set to 85 to 120 degrees.

Embossed solder masks for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a package substrate includes the solder mask with non-planar features along a surface of the solder mask such that the area of the surface is increased. The non-planar features may correspond to concave recesses formed on the surface of the solder mask. Physical dimensions (e.g., widths, depths) and/or areal densities of the non-planar features of the embossed solder masks may vary based on local areas of the package substrate exclusive of conductive bumps. The non-planar features may be formed by pressing a mold having convex features against the surface of the solder mask. The solder mask may be heated while pressing the mold against the surface of the solder mask. In some embodiments, the mold includes regions lacking the convex features.

A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of conductive members surrounded by the dielectric layer, a first conductive pillar disposed over and electrically connected with one of the plurality of conductive members, a second conductive pillar disposed over and electrically connected with one of the plurality of conductive member, a first die disposed over the RDL and electrically connected with the first conductive pillar, and a second die disposed over the RDL and electrically connected with the second conductive pillar, wherein a height of the second conductive pillar is substantially greater than a height of the first conductive pillar, and a thickness of the first die is substantially greater than a thickness of the second die.

A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.

Techniques and mechanisms for a reconstituted circuit device to be formed using a flow of material, by capillary action, in a region between a first die and a second die. In an embodiment, a rigid mass extends around, and between, the first die and the second die. The rigid mass comprises a first body of a first material, and a second body of second material, wherein the bodies each extend across the region to respective sidewall structures of the first and second dies. In the region, a portion of the first body forms a surface structure which adjoins the second body. A concave or convex shape of the surface structure is an artefact of a meniscus formed by the first material during a liquid state thereof. In another embodiment, the reconstituted circuit device further comprises an interconnect which adjoins, and extends through, the rigid mass.

A method for forming a planarization layer is provided that can include depositing an organic planarization layer on a deposition surface using a spin on deposition method; and treating the deposited organic planarization layer with a solvent anneal. In some embodiments, a vapor of solvent is passed over the deposited organic planarization layer to increase uniformity of the deposited organic planarization layer. The method may further include curing the deposited organic planarization layer with a thermal anneal.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.