In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

According to an exemplary embodiment, a semiconductor component includes a chip carrier, a semiconductor chip mounted on the chip carrier, and a chip package made of potting compound. The potting compound only partially surrounds the semiconductor chip, such that at least part of an upper side of the semiconductor chip is not covered by the potting compound. The semiconductor component further includes a clip that is mechanically connected to the upper side of the semiconductor chip.

A semiconductor package and manufacturing method is disclosed. The semiconductor package includes a semiconductor chip having a plurality of chip terminals formed on one surface thereof, a redistribution layer electrically connected to the chip terminal and extending outwardly from a side surface of the chip to electrically connect the chip terminal to an external device, an external pad provided on the insulating layer, formed to be in contact with the redistribution layer exposed from the insulating layer to be electrically connected to the redistribution layer, and exposed to an upper side of the insulating layer; an external connection terminal formed on the external pad and contacting an external device, a protective layer formed to surround at least one surface and a side surface of the chip, and an insulating layer formed to cover the redistribution layer.

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

A semiconductor package includes an interposer substrate; an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate, a chip stack on a bottom surface of the interposer substrate and including a plurality of stacked lower semiconductor chips, wherein each of the lower semiconductor chips includes a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate, a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip, and a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias. The upper semiconductor chip is electrically connected through the interposer substrate to the through vias.

A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.

Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.

A method for packaging chips includes: providing a filter wafer and a plurality of substrates to be packaged, each substrate to be packaged being provided with one or more first pads; flip-chip bonding the substrates to be packaged on the filter wafer; molding the substrates to be packaged to form a molded layer on the substrates to be packaged, the substrates to be packaged, the molded layer, and the filter wafer forming a molded structure, each substrate to be packaged, a portion of the molded layer formed on the substrate to be packaged, and the filter wafer together enclosing a cavity; exposing the first pads out of the molded layer; and cutting the molded structure into a plurality of particle chips.