A back end of line (BEOL) structure for an integrated circuit chip includes a last metal structure providing a bonding pad. A passivation structure over the bonding pad includes a first opening extending exposing an upper surface of the bonding pad. A conformal nitride layer extends over the passivation structure and is placed in contact with the upper surface of the bonding pad. An insulator material layer covers the conformal nitride layer and includes a second opening that extends through both the insulator material layer and the conformal nitride layer. A foot portion of the conformal nitride layer on the upper surface of the bonding pad is self-aligned with the second opening.

A semiconductor device package structure includes a substrate. The substrate has a circuit structure formed in a die region. The die region is defined by a plurality of scribe lines configured on the substrate. A seal ring is disposed in the substrate and located at a periphery region of the die region, and surrounds at least a portion of the circuit structure. A trench ring is disposed in the substrate between the seal ring and the scribe lines. A packaging passivation cap layer covers over the circuit structure and the seal ring, and covers at least the trench ring.

In a semiconductor device, a semiconductor element includes a semiconductor substrate, a surface electrode and a protective film. The semiconductor substrate has an active region and an outer peripheral region. The surface electrode includes a base electrode disposed on a front surface of the semiconductor substrate and a connection electrode disposed on the base electrode. The protective film covers a peripheral end portion of the base electrode and an outer peripheral edge of the connection electrode. The protective film has an opening to expose the connection electrode so as to enable a solder connection. A boundary between the outer peripheral edge of the connection electrode and the protective film is located at a position corresponding to the outer peripheral region in a plan view.

A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.

A transistor device includes a substrate, a semiconductor structure on the substrate, a metallization layer comprising a non-planar surface on a surface of the semiconductor structure, a non-planar encapsulation layer on the non-planar surface of the metallization layer, the non-planar encapsulation layer comprising a non-planar encapsulant surface that is opposite the non-planar surface, and a self-planarizing encapsulation layer on the non-planar encapsulation layer and comprising a planarized surface that is opposite the non-planar encapsulant surface.

A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.

A method includes forming a first substrate including a first dielectric layer and a first metal pad, forming a second substrate including a second dielectric layer and a second metal pad, and bonding the first dielectric layer to the second dielectric layer, and the first metal pad to the second metal pad. One or both of the first and second substrates is formed by forming a first insulating layer, forming an opening in the layer, forming a barrier on an inner surface of the opening, forming a metal pad material on the barrier, polishing the metal pad material to expose a portion of the barrier and to form a gap, expanding the gap, forming a second insulating layer to fill the opening and the gap, and polishing the insulating layers such that a top surface of the metal pad is substantially planar with an upper surface of the polished layer.

A semiconductor die includes a semiconductor body having a gate, a source contact, and a drain contact thereon, a metal contact structure on the semiconductor body and electrically connected to the gate, the source contact, or the drain contact, and an encapsulation structure. The encapsulation structure includes first and second encapsulation layers of respective non-conductive materials stacked on the metal contact structure, and an opening extending therethrough to expose the metal contact structure. The opening includes a sidewall having a substantially continuous slope that extends through the first and second encapsulation layers to the metal contact structure. Related devices and fabrication methods are also discussed.

A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.