In some embodiments, an integrated chip (IC) is provided. The IC includes a metallization structure disposed over a semiconductor substrate, where the metallization structure includes an interconnect structure disposed in an interlayer dielectric (ILD) structure. A passivation layer is disposed over the metallization structure, where an upper surface of the interconnect structure is at least partially disposed between opposite inner sidewalls of the passivation layer. A sidewall spacer is disposed along the opposite inner sidewalls of the passivation layer, where the sidewall spacer has rounded sidewalls. A conductive structure is disposed on the passivation layer, the rounded sidewalls of the sidewall spacer, and the upper surface of the interconnect structure.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, and a passivation layer, where the passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate the passivation layer and expose the heterostructure layer; a second semiconductor layer, where the second semiconductor layer is located in the first groove, and the second semiconductor layer does not fully fill the first groove in a horizontal direction; a first electrode, where the first electrode is at least located on a heterostructure layer and the second semiconductor layer that are corresponding to the first groove; and a second electrode located in the second groove.

According to the present disclosure, a semiconductor device includes a semiconductor substrate, a first metal layer provided above the semiconductor substrate, a second metal layer provided above the first metal layer and containing Ni as a material and a third metal layer provided above the second metal layer and containing Cu or Ni as a material, wherein the second metal layer has a Vickers hardness of 400 Hv or more and is harder than the third metal layer, and the third metal layer is harder than the first metal layer.

A transistor device includes a substrate, a gate contact pad on the substrate, and a transistor die on the substrate adjacent the gate contact pad. The transistor die includes an active region and a gate bond pad adjacent the active region, and the gate bond pad has a side edge adjacent the active region that extends in a first direction. The transistor device includes a bonding wire bonded to the gate contact pad at a first end of the bonding wire and to the gate bond pad at a second end of the bonding wire. The bonding wire extends in a second direction that is oblique to the first direction such that the bonding wire forms an angle relative to the first direction that is less than 90 degrees.

An integrated circuit structure includes a semiconductor substrate, a passivation layer, a first protective layer, and a second protective layer. The passivation layer is over the semiconductor substrate. The first protective layer is over the passivation layer. The second protective layer is over the first protective layer, wherein a boundary of the first protective layer is confined within the second protective layer.

An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.

A semiconductor device includes a first semiconductor die mounted on a substrate, a second semiconductor die mounted on the substrate and separated from the first semiconductor die, a first dielectric material between the first semiconductor die and the second semiconductor die and having a first density, and a column of second dielectric material in the first dielectric material, the second dielectric material having a second density different than the first density, and the second dielectric material including a void region.