Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

Structures and formation methods of a chip package structure are provided. The chip package structure includes an interposer substrate including first and second die regions that are separated by a gap region. The chip package structure also includes first and second semiconductor dies respectively arranged over the first and second die regions. In addition, the chip package structure includes first and second gap-filling layers formed over the gap region and separated from one another, and a third gap-filling layer over the gap region and between the first and second gap-filling layers. The Young's modulus of the third gap-filling layer is less than the Young's modulus of the first gap-filling layer and the Young's modulus of the second gap-filling layer.

A semiconductor package includes a substrate, a first insulation layer, a conductive via and a conductive trace. The substrate includes a conductive component. The first insulation layer is formed on the substrate and having a first through hole exposing the conductive component. The conductive via is formed within the first through hole. The conductive trace is directly connected to the conductive via which is located directly above the first through hole.

The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.

The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

A semiconductor device includes: a device formed in a III-V semiconductor body; metal layer(s) above the III-V semiconductor body; an interlayer dielectric adjacent each metal layer; vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; a passivation layer touching and being supported by a top surface of the III-V semiconductor body, the lowermost interlayer dielectric touching and being supported by a top surface of the passivation layer, the passivation layer being an ineffective barrier against diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body; and a barrier interposed between a first oxide layer and a second oxide layer of the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the first oxide layer of the lowermost interlayer dielectric and which is immediately below the barrier.

A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound.