A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.

A semiconductor device includes: an emitter electrode being a metal electrode disposed on a semiconductor substrate; a first passivation film made of a material other than an organic resin, and covering a portion of the emitter electrode; and a second passivation film made of the organic resin, and covering a portion of the emitter electrode via the first passivation film. A copper electrode connected to a portion of the emitter electrode not covered with the first passivation film and including copper as a major component is disposed over the emitter electrode. The second passivation film and the copper electrode are spaced apart.

A semiconductor device has a semiconductor wafer and a first conductive layer formed over the semiconductor wafer as contact pads. A first insulating layer formed over the first conductive layer. A second conductive layer including an interconnect site is formed over the first conductive layer and first insulating layer. The second conductive layer is formed as a redistribution layer. A second insulating layer is formed over the second conductive layer. An opening is formed in the second insulating layer over the interconnect site. The opening extends to the first insulating layer in an area adjacent to the interconnect site. Alternatively, the opening extends partially through the second insulating layer in an area adjacent to the interconnect site. An interconnect structure is formed within the opening over the interconnect site and over a side surface of the second conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is formed to cover the first film (3) and second film (4). After forming the surface protection film (5), a reverse surface of the semiconductor wafer (1) is etched with a chemical liquid. The first film (3) is formed on an outer peripheral section of the semiconductor wafer (1). The second film (4) is not formed on the outer peripheral section of the semiconductor wafer (1). The first film (3) and the surface protection film (5) are adhered to each other in the outer peripheral section of the semiconductor wafer (1). The first film (3) has a higher adhesion to the surface protection film (5) than the second film (4).

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via.

An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes. Each probe pad includes a plurality of lower level conductor layers arranged in lower level conductor frames, a plurality of lower level vias extending vertically through lower level insulator layers and electrically coupling the lower level conductor frames; a plurality of upper level conductor layers, each forming two portions on two outer edges of the probe pad, the two portions aligned with, spaced from, and on opposite sides of the saw kerf lane, the coverage of the upper level conductor layers being less than about twenty percent; and a plurality of upper level vias extending vertically through upper level insulator layers and coupling the upper level conductor layers electrically to one another and to the lower level conductor layers. Methods are disclosed.

A method includes bonding a first wafer to a second wafer, performing a trimming process on the first wafer, and depositing a sidewall protection layer contacting a sidewall of the first wafer. The depositing the sidewall protection layer includes depositing a high-density material in contact with the sidewall of the first wafer. The sidewall protection layer has a density higher than a density of silicon oxide. The method further includes removing a horizontal portion of the sidewall protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

A method for manufacturing a composite layer circuit structure of an electronic device is provided. First, a first conductive layer is formed on a carrier plate. Next, a first photoresist layer is formed on the first conductive layer. The first photoresist layer includes multiple first openings exposing part of the first conductive layer. Next, a first electroplating layer is formed in the first openings. Then, the first photoresist layer is removed. Then, a first insulating layer is formed on the first conductive layer. The first insulating layer includes multiple second openings exposing part of the first electroplating layer. In the above, at least one heat treatment process is performed on the first electroplating layer before the first insulating layer is formed on the first conductive layer. A temperature when performing at least one heat treatment process is higher than or equal to 40° C. and lower than or equal to 300° C.

An integrated fan-out package including an integrated circuit, an insulating encapsulation, a plurality of conductive through vias, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The insulating encapsulation encapsulates sidewalls of the integrated circuit. The conductive through vias penetrate in the insulating encapsulation. The redistribution circuit structure is disposed on the integrated circuit, the conductive through vias and the insulating encapsulation. The redistribution conductive layer is electrically connected to the conductive terminals and the conductive through vias. A plurality of first contact surfaces of the conductive terminals and a plurality of second contact surfaces of the conductive through vias are in contact with the redistribution circuit structure, and a roughness of the first contact surfaces and the second contact surfaces ranges from 100 angstroms to 500 angstroms. Methods of fabricating the integrated fan-out package are also provided.