A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

A crack stopper structure in an electronic device is provided. The crack stopper structure in an electronic device includes at least two non-recesses and a recess. The recess is disposed between the at least two non-recesses. In addition, the recess is greater than each of the at least two non-recesses in width.

An advanced moisture resistant structure of compound semiconductor integrated circuit comprises a compound semiconductor substrate, a compound semiconductor epitaxial structure, a compound semiconductor integrated circuit and a moisture barrier layer. The compound semiconductor epitaxial structure is formed on the compound semiconductor substrate. The compound semiconductor integrated circuit is foimed on the compound semiconductor epitaxial structure. The moisture barrier layer is formed on the compound semiconductor integrated circuit. The moisture barrier layer is made of A1.sub.2O.sub.3. The thickness of the moisture barrier layer is greater than or equal to 400 Å and less than or equal to 1000 Å so as to enhance the moisture resistant ability of the compound semiconductor integrated circuit.

Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

An electronic device, comprising: a semiconductor body of silicon carbide; an insulating layer on a surface of the semiconductor body; a layer of metal material extending in part on the surface of the semiconductor body and in part on the insulating layer; a SiN interface layer on the layer of metal material and the insulating layer; a passivation layer on the interface layer; and an anchoring element that protrudes from the passivation layer towards the first insulating layer and extends in the first insulating layer underneath the interface layer.

A semiconductor structure includes a conductive structure over a first passivation layer. The semiconductor structure further includes a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer includes a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

An electronic device comprising: a semiconductor body of silicon carbide; a first insulating layer on a first surface of the semiconductor body, of a first material with electrical-insulator or dielectric characteristics; a first layer of metal material extending in part on the first surface of the semiconductor body and in part on the first insulating layer; an interface layer on the first layer of metal material and on the first insulating layer, of a second material different from the first material; and a passivation layer of the first material on the interface layer. The first material is silicon oxide, and the second material is silicon nitride.

The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

A semiconductor device includes an interconnect structure disposed over a first semiconductor die. The first semiconductor die includes a semiconductor substrate and a first conductive pad disposed over the semiconductor substrate, and the first conductive pad is covered by the interconnect structure. The semiconductor device also includes dielectric spacers surrounding the interconnect structure. An interface between the dielectric spacers and the interconnect structure is curved. The semiconductor device further includes a dielectric layer surrounding the dielectric spacers, and a second semiconductor die bonded to the dielectric layer and the interconnect structure. The second semiconductor die includes a second conductive pad, and the interconnect structure is covered by the second conductive pad.