Patent classifications
H01L23/3677
STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES
A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure.
FLIP CHIP CIRCUIT
A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
The present disclosure is directed to a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technologies. The semiconductor device includes a fin ESD element. The method includes: providing a substrate structure, where the substrate structure includes a semiconductor substrate, and a semiconductor fin for the fin ESD element and an electrode structure surrounding a part of the semiconductor fin that are on the semiconductor substrate; forming a second dielectric layer on the substrate structure to cover the electrode structure; forming, in the second dielectric layer, a trench extending to a top of the electrode, where the trench is on the electrode and extends along a longitudinal direction of the electrode, and a transverse width of the trench is less than or equal to a transverse width of the top of the electrode; and filling the trench with a metal material, so as to form a metal heat sink that is on the top of the electrode and is coupled to the electrode. With the present disclosure, an existing structure of an ESD element is improved, so that a metal heat sink can effectively improve a head dissipation effect of a device, thereby improving a performance of the device.
METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS
Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods.
Semiconductor Devices and Methods of Formation Thereof
In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.
Semiconductor device and method of forming micro interconnect structures
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
Heat conduction pattern for cooling a power module
A semiconductor module includes: a switching device including a gate pad; an output unit including an output pad connected with the gate pad of the switching device through a wire and outputting a drive signal from the output pad to the switching device; a temperature protection circuit detecting temperature and performing protection operation; and a heat conduction pattern connected with the output pad, extending from the output pad toward the temperature protection circuit, and conducting heat generated at the switching device to the temperature protection circuit.
Thermal management of three-dimensional integrated circuits
A 3D integrated circuit device can include a substrate, a thermal interface layer and at least one die, at least one device layer bonded between the thermal interface layer and the at least one die, wherein the thermal interface layer enhances conductive heat transfer between the at least one device layer and the at least one die, and a heat sink located adjacent to a heat spreader, wherein the thermal interface layer, the at least one die and the at least one device layer are located between the heat spreader and the substrate.
HEAT SINK, HEAT SINK ARRANGEMENT AND MODULE FOR LIQUID IMMERSION COOLING
Heat sink and heat sink arrangements are provided for an electronic device immersed in a liquid coolant. A heat sink may comprise: a base for mounting on top of a heat-transmitting surface of the electronic device and transferring heat from the heat-transmitting surface; and a retaining wall extending from the base and defining a volume. A heat sink may have a wall arrangement to define a volume, in which the electronic device is mounted. A heat sink may be for an electronic device to be mounted on a surface in a container, in an orientation that is substantially perpendicular to a floor of the container. Heat is transferred from the electronic device to liquid coolant held in the heat sink volume. A cooling module comprising a heat sink is also provided. A nozzle arrangement may direct liquid coolant to a base of the heat sink.
Exfoliated graphite materials and composite materials and devices for thermal management
Exfoliated graphite materials, and composite materials including exfoliated graphite, having enhanced through-plane thermal conductivity can be used in thermal management applications and devices. Methods for making such materials and devices involve processing exfoliated graphite materials such as flexible graphite to orient or re-orient the graphite flakes in one or more regions of the material.