A direct to chip cooling film for two-phase cooling. The film includes a dielectric layer having a first surface for attachment to a cold plate or circuits and having a second surface. A metal layer is on the second surface of the dielectric layer with a pattern of features on a side opposite the dielectric layer. This surface pattern provides increased surface area and multiple nucleation sites for bubbles formation for two-phase cooling. The features can also include metal nodules to further enhance the nucleation.

A device, and method of operating the device, are disclosed. The device includes: a heat spreader having a first side and a second side opposite the first side, the heat spreader including at least one oscillating heat pipe arranged between the first side and the second side, at least one of the at least one oscillating heat pipe including a plurality of interconnected channels including a working fluid; at least one optoelectronic component coupled to the first side of the heat spreader; and at least one thermoelectric cooler, wherein a cold side of the at least one thermoelectric cooler is coupled to the second side of the heat spreader. The heat spreader may include one or more heat exchange features.

The purpose of the present invention is to provide a sandwich structure that has both excellent heat dissipation properties and excellent mechanical properties. In order to achieve this purpose, the sandwich structure of the present invention has the following structure. The sandwich structure includes a core member (I), and a fiber reinforced member (II) disposed on both sides of the core member (I), wherein the core member (I) includes a sheet-shaped heat conductive member (III) having an in-plane thermal conductivity of 300 W/m.K or more.

Exemplary package on package (PoP) assemblies may include a substrate. The PoP assemblies may include a first package positioned on a first side of the substrate with a bottom surface of the first package facing the substrate. The PoP assemblies may include a second package positioned on a second side of the substrate with a top surface of the second package facing the substrate. The second side may be positioned opposite the first side. The PoP assemblies may include a conductive element that contacts one or both of a top surface and the bottom surface of the second package and extends to a position that is aligned with or above a top surface of the first package.

Provided are a heat dissipation structure and a heat dissipation system. The heat dissipation structure includes a heat dissipation channel and a plurality of heat dissipation fins. The plurality of heat dissipation fins are arranged on at least one side of the heat dissipation channel. Heat dissipation fins arranged on the same side of the heat dissipation channel are arranged along an extension direction of the heat dissipation channel. The heat dissipation channel and the plurality of heat dissipation fins are each formed as a cavity structure. Each heat dissipation fin includes a first end and a second end arranged opposite to each other. The first end is a closed end, and the second end is an open end. The second end communicates with the heat dissipation channel.

A composite structure includes a first metal layer, a second metal layer, and a ceramic layer disposed therebetween. The ceramic layer has a first surface and a second surface opposite to each other and is adapted to absorb electromagnetic waves. The absorbance reaction range of the electromagnetic waves by the ceramic layer ranges from 100 MHz to 400 GHz. The first metal layer has an opening exposing the second surface. An inner sidewall of the first metal layer surrounds the opening. The orthographic projection of the second metal layer on the ceramic layer at least partially overlaps the orthographic projection of the opening on the ceramic layer. The thickness ratio of the first metal layer to the second metal layer is 1:1 to 1:2. The area ratio of the first metal layer to the second metal layer is 1:1.2 to 1:4. A package architecture including the composite structure is also provided.

A semiconductor packaging structure includes: a substrate, a redistribution layer having one conductive plugs, metal bumps disposed on the redistribution layer, and electrically connected with the redistribution layer including the conductive plug; a semiconductor chip over the redistribution layer and aligned to and electrically connected with the conductive plug; an underfill layer filling a gap between the redistribution layer and the semiconductor chip and the conductive plugs; a polymer layer on the redistribution layer, over the plurality of metal bumps, the underfill layer and the semiconductor chip, exposing only top parts of the plurality of metal bumps and top part of the semiconductor chip; and an antenna module disposed on the second surface of the substrate.

A semiconductor package structure having an antenna module includes: a substrate, having a first surface and a second surface; a semiconductor chip, disposed on the first surface; a plastic packaging material layer, formed on the first surface, where the plastic packaging material layer wraps the semiconductor chip and exposes a part of a front surface of the semiconductor chip; a rewiring layer, disposed on the plastic packaging material layer and electrically connected to the semiconductor chip; a metal bump, electrically connected to the rewiring layer; and an antenna module, disposed on the second surface of the substrate.

A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

A monolithic substrate including a silica material fused to bulk copper is provided for coupling with electronic components, along with methods for making the same. The method includes arranging a base mixture in a die mold. The base mixture includes a bottom portion with copper micron powder and an upper portion with copper nanoparticles. The method includes arranging a secondary mixture on the upper portion of the base mixture. The secondary mixture includes a bottom portion with silica-coated copper nanoparticles and an upper portion with silica nanoparticles. The method includes heating and compressing the base mixture and the secondary mixture in the die mold at a temperature, pressure, and time sufficient to sinter and fuse the base mixture with the secondary mixture to form a monolithic substrate. The resulting monolithic substrate defines a first major surface providing thermal conductivity, and a second major surface providing an electrically resistive surface.