A metal-silicon carbide-based composite material including: a composite part including a silicon carbide-based porous body constituted by a plurality of silicon carbide particles, and a metal that is infiltrated in the silicon carbide-based porous body; and first and second surface layers which contain a metal, and coat both main surfaces of the composite part. The metal contains at least one kind selected from the group consisting of aluminum and magnesium, and the amount of particles having a particle size of 300 μm or more in the plurality of silicon carbide particles is 5% by volume or less.

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

A silicon interconnect fabric includes: (1) a substrate having a front side and a back side; (2) a front side patterned metal layer on the front side of the substrate; (3) a back side patterned metal layer on the back side of the substrate; (4) multiple conductive vias extending through the substrate and connecting the front side patterned metal layer and the back side patterned metal layer; and (5) multiple conductive posts connected to the back side patterned metal layer.

Some embodiments may include a porous silicon carbide substrate plugged with dielectric material, the porous silicon carbide substrate including a first side to couple to a heat source and a second side to couple to an electrically conductive surface, wherein the second side is opposite the first side; wherein in the case that an opening on the area of the first side forms a channel with an opening on an area of the second side, a portion of the dielectric material located in the channel is arranged to prevent an electrical short from forming through the porous silicon carbide substrate to the electrically conductive surface. In some examples, the heat source may be one or more semiconductor laser diode chips. Other embodiments may be disclosed and/or claimed.

A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

A semiconductor package may include a package substrate, an interposer, a logic chip, at least one memory chip and a heat sink. The interposer may be located over an upper surface of the package substrate. The interposer may be electrically connected with the package substrate. The logic chip may be located over an upper surface of the interposer. The logic chip may be electrically connected with the interposer. The memory chip may be located over an upper surface of the interposer. The memory chip may be electrically connected with the interposer and the logic chip. The heat sink may make thermal contact with the upper surface of the logic chip to dissipate heat in the logic chip.

A semiconductor device including a first semiconductor die, a second semiconductor die, thermal silicon substrates and an encapsulation is provided. The second semiconductor die is disposed on and electrically connected to the first semiconductor die. The thermal silicon substrates are disposed on the first semiconductor die, wherein the thermal silicon substrates are spaced apart from the second semiconductor die. The encapsulation is disposed on the first semiconductor die. The encapsulation encapsulates the second semiconductor die and the thermal silicon substrates. The encapsulation includes a filling material layer and an insulator, wherein the filling material layer is disposed on the first semiconductor die and located between the second semiconductor die and thermal silicon substrates, and the filling material layer is spaced apart from the second semiconductor die and the thermal silicon substrates by the insulator.