Patent classifications
H01L23/3738
Semiconductor microcooler
A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.
Semiconductor structures having reduced thermally induced bow
A Monolithic Microwave Integrated Circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.
Multi layer thermal interface material
A multi-layer thermal interface material including two or more thermal interface materials laminated together, where each of the two or more thermal interface materials comprise different mechanical properties.
THERMALLY CONDUCTIVE SLUGS/ACTIVE DIES TO IMPROVE COOLING OF STACKED BOTTOM DIES
Embodiments include semiconductor packages. A semiconductor package includes first and second bottom dies on a package substrate, first top dies on the first bottom die, and second top dies on the second bottom die. The semiconductor package includes thermally conductive slugs on the first bottom die and the second bottom die. The thermally conductive slugs are comprised of a high thermal conductive material. The thermally conductive slugs are positioned directly on outer edges of top surfaces of the first and second bottom dies, inner edges of the top surfaces of the first and second bottom dies, and/or a top surface of the package substrate. The high thermal conductive material of the thermally conductive slugs is comprised of copper, silver, boron nitride, or graphene. The thermally conductive slugs may have two different thicknesses. The semiconductor package may include an active die and/or an integrated heat spreader with the pedestals.
Semiconductor structure and fabrication method thereof
A method for fabricating a semiconductor structure includes providing a substrate and forming a plurality of fins on a surface of the substrate. Along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions. The first regions are located at both sides of the second regions. The method also includes forming first openings in the fins by removing the first regions of the fins at both sides of the gate structures until the substrate is exposed. Further, the method includes forming thermal conductive layers in the first openings, and forming doped layers on top surfaces of the thermal conductive layers. A material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, and the second thermal conductivity is larger than the first thermal conductivity.
Integrated circuit package and method of forming same
A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.
Tailored coldplate geometries for forming multiple coefficient of thermal expansion (CTE) zones
An apparatus includes a coldplate configured to be thermally coupled to a structure to be cooled and to remove thermal energy from the structure. The coldplate includes (i) first and second outer layers having at least one first material and (ii) a third layer embedded in the outer layers and having at least one second material. The first and second materials have different coefficients of thermal expansion (CTEs). The third layer is embedded non-uniformly in the outer layers so that different zones of the coldplate have different local CTEs. The third layer may include openings extending through the second material(s), and projections of the first material(s) from at least one of the first and second outer layers may partially or completely fill the openings. The first and second outer layers may include aluminum or an aluminum alloy, and the third layer may include aluminum silicon carbide or thermal pyrolytic graphite.
DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS
Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.
Composite material, electronic apparatus, and method for manufacturing electronic apparatus
A composite material includes a base resin, a heat dissipation filler that is mixed into the base resin, hollow particles that are mixed into the base resin, hollow particles that are mixed into the base resin, and bubbles that are formed in the base resin.
SEMICONDUCTOR STRUCTURES HAVING REDUCED THERMALLY INDUCED BOW
A Monolithic Microwave Integrated Circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.