Patent classifications
H01L23/4012
MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES
A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.
INTEGRATED CIRCUITS AND METHODS FOR FORMING INTEGRATED CIRCUITS
An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
Heat conduction structure or semiconductor apparatus
The disclosure provides a heat conduction structure with higher heat conductivity. This embodiment is a heat conduction structure where heat is conducted from a first member to a second member. The heat conduction structure includes at least one self-assembled monolayer and a heat dissipation grease. The self-assembled monolayer is formed on at least one surface of the first member and the second member. The heat dissipation grease is disposed between the first member and the second member. The heat dissipation grease is in contact with the self-assembled monolayer.
HEAT DISSIPATION PLATE FOR CHIP HEAT DISSIPATION, SERVER HEAT DISSIPATION SYSTEM, AND HEATING DEVICE
The present disclosure discloses a heat dissipation plate for chip heat dissipation, a server heat dissipation system, and a heating device. One end of the heat dissipation plate may be blocked. Another end of the heat dissipation plate may be provided with a water inlet and a water outlet. A pipeline assembly in the heat dissipation plate may include a plurality of branch water inlet pipelines and a plurality of branch outlet pipelines. One end of the plurality of branch water inlet pipelines may operably connect to the water inlet. One end of the plurality of branch water outlet pipelines may operably connect to the water outlet. Another end of the plurality of branch water inlet pipelines may be operably connected to another end of the plurality of branch water outlet pipelines through a connection pipeline.
Semiconductor package having leads with a negative standoff
A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. The bottom surface of each lead of the plurality of leads is coplanar with the bottom main surface of the mold compound or disposed in a plane above the bottom main surface of the mold compound so that no lead of the plurality of leads extends below the bottom main surface of the mold compound.
Self-healing PDMS encapsulation and repair of power modules
A power electronics assembly is provided with a self-healing feature. The power electronics assembly may include a semiconductor electronics device and an insulating substrate coupled to the semiconductor electronics device. A base metal structural component may be provided, coupled to the insulating substrate. The assembly may include a frame component cooperating with the base metal structural component and defining an enclosure containing the semiconductor electronics device and the insulating substrate. The assembly further includes a self-healing polymer comprising disulfide bonds. The self-healing polymer is disposed within the enclosure; additional potting material may also be provided as a multi-layered encapsulation. In various aspects, the self-healing polymer may include polydimethylsiloxane based polyurethane (PDMS-PU) modified with disulfide bonds. The frame component may be configured to direct or confine heat to areas of the assembly where ESD may be problematic.
IPD modules with flexible connection scheme in packaging
A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package.
Semiconductor Package and Method
A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.
Semiconductor device and manufacturing method of the same
A semiconductor device includes a semiconductive substrate, a dielectric stack disposed over the semiconductive substrate, a probe pad formed on the dielectric stack, a test key embedded in the semiconductor device and a single via string stacking extending along a direction from a level of the probe pad to the semiconductive substrate and electrically connecting the periphery of the probe pad to the test key. A semiconductor device includes a semiconductive substrate, a dielectric stack, a probe pad, a test key, an extension segment electrically connected to the periphery of the probe pad and laterally extending from the probe pad from a top view, and a single via string stacking extending along a direction from the probe pad to the semiconductive substrate and electrically connecting the extension segment to the test key. The single via string stacking and the probe pad are laterally offset from a top view.
Pressing member
A pressing member is used for pressing semiconductor modules and cooling pipes which are alternately disposed, and includes a plate and an elastic member. The plate includes a contact plate section that faces an end surface of the fixed unit in the fixed direction and contacts with the end surface of the fixed unit, and plate ribs standing in the fixed direction from an end portion of the contact plate section in a width direction of the contact plate section. The elastic member is disposed in a side of the plate opposite to a side of the plate where the fixed unit is disposed, the elastic member pressing the plate towards a fixed unit side in the fixed direction. The contact plate section has an inner plate surface including a concave surface formed at a portion apart from the plate ribs in a contact region.