Disclosed is a low-profile microdisplay module that comprises a package substrate, a microdisplay chip disposed over a first surface of the package substrate, and a plurality of conductive vias. The plurality of conductive vias are electrically coupled to the microdisplay chip and disposed through the package substrate to a second surface of the package substrate, the second surface being opposite and parallel to the first surface. The microdisplay module further comprises a flexible flat circuit connector coupled to the plurality of conductive vias at the second surface of the package substrate.

A lighting apparatus using an organic light-emitting diode and a method of fabricating the same are characterized in that an organic emissive material and a conductive film used as a cathode are deposited on the entire surface of a substrate, and then an organic emissive layer in a lighting area and contact areas becomes separated (disconnected or cut) by laser ablation, simultaneously with the formation of a contact hole for contact with an anode. Next, cathode contact and encapsulation processes are performed using an adhesive containing conductive particles and a metal film. This simplifies the fabrication process of the lighting apparatus without using an open mask (metal mask), which is a complicated tool, thus making it useful especially in roll-to-roll manufacturing.

The invention relates to a method for electrically contacting a component (10) (for example a power component and/or a (semiconductor) component having at least one transistor, preferably an IGBT (insulated-gate bipolar transistor)) having at least one contact (40, 50), at least one open-pored contact piece (60, 70) is galvanically (electrochemically or free of external current) connected to at least one contact (40, 50). In this way, a component module is achieved. The contact (40, 50) is preferably a flat part or has a contact surface, the largest planar extent thereof being greater than an extension of the contact (40, 50) perpendicular to said contact surface. The temperature of the galvanic connection is at most 100 C., preferably at most 60 C., advantageously at most 20 C. and ideally at most 5 C. and/or deviates from the operating temperature of the component by at most 50 C., preferably by at most 20 C., in particular by at most 10 C. and ideally by at most 5 C., preferably by at most 2 C. The component (10) can be contacted by means of the contact piece (60, 70) with a further component, a current conductor and/or a substrate (90). Preferably, a component (10) having two contacts (40, 50) on opposite sides of the component (10) is used, wherein at least one open-pored contact piece (60, 70) is galvanically connected to each contact (40, 50).

Provided are a chip-on-film (COF) semiconductor package capable of improving connection characteristics and a display apparatus including the package. The COF semiconductor package includes a film substrate, a conductive interconnection located on at least one surface of the film substrate and an output pin connected to the conductive interconnection and located at one edge on a first surface of the film substrate, a semiconductor chip connected to the conductive interconnection and mounted on the first surface of the film substrate, a solder resist layer on the first surface of the film substrate to cover at least a portion of the conductive interconnection, and at least one barrier dam on the solder resist layer between the semiconductor chip and the output pin.

A semiconductor device includes an assembly configured such that a plurality of semiconductor modules is connected by a component. Each of the plurality of semiconductor modules includes a semiconductor element including a front-surface electrode fixing a front-surface electrode plate and a back-surface electrode fixing a back-surface electrode plate, wherein the component is either of a first component and a second component. The first component being configured to connect adjacent semiconductor modules to each other such that a front-surface electrode plate of one of the adjacent semiconductor modules is connected to a back-surface electrode plate of the other one of the adjacent semiconductor modules. The second component is configured to connect adjacent semiconductor modules such that respective front-surface electrode plates are connected and respective back-surface electrode plates are connected. The semiconductor modules are connected by the first component or the second component.

A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.

A method of forming In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate.

A substrate structure includes a first substrate, a plurality of first bonding pads, a second substrate and a connecting layer. The first substrate has an element configuration area and a peripheral area. The peripheral area is located around the element configuration area. The first bonding pads are configured spacing at the peripheral area, and a gap is provided between two adjacent first bonding pads. The first bonding pads are located between the first substrate and the second substrate. The connecting layer is located between the first bonding pads and the second substrate. The part of the connecting layer close to the element configuration area is configured with a plurality of first arc edges.

A dual-side cooling (DSC) semiconductor package includes a first metal-insulator-metal (MIM) substrate having a first insulator layer, first metallic layer, and second metallic layer. A second MIM substrate includes a second insulator layer, third metallic layer, and fourth metallic layer. The third metallic layer includes a first portion having a first contact area and a second portion, electrically isolated from the first portion, having a second contact area. A semiconductor die is coupled with the second metallic layer and is directly coupled with the third metallic layer through one or more solders, sintered layers, electrically conductive tapes, solderable top metal (STM) layers, and/or under bump metal (UBM) layers. The first contact area is electrically coupled with a first electrical contact of the die and the second contact area is electrically coupled with a second electrical contact of the die. The first and fourth metallic layers are exposed through an encapsulant.