In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of t.sub.press1>t.sub.cast1 and t.sub.press2>t.sub.cast1, where t.sub.press1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, t.sub.press2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and t.sub.cast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.

Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, a first encapsulant covering at least portions of the inactive surface and a side surface of the semiconductor chip, a connection structure having first and second regions disposed sequentially on the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and including a ground pattern layer, and a metal layer disposed on the upper surface of the first encapsulant, and extending from the upper surface of the first encapsulant to the side surface of the first region of the connection structure. The first region of the connection structure has a first width, and the second region has a second width, smaller than the first width.

A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

One aspect relates to a method for producing a circuit carrier for a semiconductor component. At least one first copper layer or one first copper-alloy layer with a first coefficient of expansion and at least one second layer made from a second material of low expandability with a second coefficient of expansion, which is smaller than the first coefficient of expansion, are bonded to one another by means of a low-temperature sintering method at a bonding temperature of 150° C. to 300° C.

Methods of forming semiconductor packages include providing a first insulator layer coupled with a first metallic layer. A recess is formed in the first metallic layer and a semiconductor die is mechanically coupled therein. The die is mechanically coupled with a second metallic layer and the second metallic layer is coupled with a second insulator layer. The die and layers are at least partially encapsulated to form the semiconductor package. The first and/or second metallic layers may be insulator-metal substrates, metal-insulator-metal (MIM) substrates, or may be formed of lead frames. In implementations the package does not include a spacer between the die and the first metallic layer and does not include a spacer between the die and the second metallic layer. In implementations the first insulator layer and the second insulator layer are exposed through the encapsulant or are mechanically coupled with metallic layers exposed through the encapsulant.

A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a ceramic tile, and assembling a precursor assembly of a direct bonded copper (DBC) substrate by coupling a first leadframe on the sinter precursor material layer on the first surface of the ceramic tile and a second leadframe on the second surface of the sinter precursor material layer on a second surface of the ceramic tile such that the ceramic tile is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first leadframe and the second leadframe to the ceramic tile to form a sinter bonded DBC substrate.

A package module includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and having a connection pad electrically connected to the one or more redistribution layers, a plurality of electronic components disposed on the connection structure and electrically connected to the one or more redistribution layers, one or more frames disposed on the connection structure, and an encapsulant disposed on the connection structure, and respectively covering at least portions of the semiconductor chip, the plurality of electronic components, and the one or more frames. At least a portion of an outer side surface of the encapsulant is coplanar on the same level as at least a portion of an outer side surface of at least one of the one or more frames.

An electronic component is provided that includes multiple conductive terminals and an insulator integrated with the conductive terminals. A leg part possessed by one of the conductive terminals and a leg part possessed by another one of the conductive terminals are disposed so as to vertically overlap each other. The leg part possessed by one of the conductive terminals and the leg part possessed by another one of the conductive terminals have different lengths, and the tip of the shorter leg part of the two is covered by a thick part of the insulator.