H01L23/4985

Chip-on-film packages and display apparatuses including the same

A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.

METHODS AND DEVICES USING MICROCHANNELS FOR INTERCONNECTIONS

A pattern of microchannels is formed on a major surface of a substrate on the side opposite an adhesive surface thereof. Through holes extend through the substrate and are connected to the pattern of microchannels. Solid circuit dies are adhesively bonded to the adhesive surface of the substrate. The contact pads of the solid circuit dies at least partially overlie and face the through holes. Electrically conductive channel traces are formed to electrically connect to the solid circuit dies via the through holes.

FLEXIBLE PRINTED CIRCUIT BOARD, COF MODULE, AND ELECTRONIC DEVICE COMPRISING THE SAME
20230057668 · 2023-02-23 ·

A flexible printed circuit board according to an embodiment includes a substrate, a circuit pattern disposed on the substrate, and a protective layer on the circuit pattern, wherein the substrate includes a chip mounting region, the circuit pattern includes a first circuit pattern and a second circuit pattern connected to a chip of the chip mounting region, the second circuit pattern includes a plurality of second wiring portions and a third pad portion and a fourth pad portion connected to the second wiring portion, the second wiring portion includes a first wiring region connected to the fourth pad portion and a second wiring region bent in the first wiring region, a first space of the first wiring region is greater than a second space of the second wiring region, and a length of the first wiring region is 100 .Math.m or more.

Sidewall Connections and Button Interconnects for Molded SiPs

Electronic modules and methods of fabrication are described. In an embodiment, an electronic module includes a molded system-in-package, and a flexible circuit mounted on a side surface of a molding compound layer such that the flexible circuit is in electrical contact with a lateral interconnect exposed along the side surface of the molding compound layer.

FLIP CHIP AND CHIP PACKAGING STRUCTURE
20220367328 · 2022-11-17 ·

The present disclosure relates to a flip-chip and a chip packaging structure. The flip-chip includes: a driver chip having a package surface facing a wiring substrate; and a plurality of conductive connectors. Any one of the plurality of conductive connectors includes a conductive bump connected to the package surface and a conductive extension portion on a side of the conductive bump away from the driver chip.

Flexible device including conductive traces with enhanced stretchability

Flexible devices including conductive traces with enhanced stretchability, and methods of making and using the same are provided. The circuit die is disposed on a flexible substrate. Electrically conductive traces are formed in channels on the flexible substrate to electrically contact with contact pads of the circuit die. A first polymer liquid flows in the channels to cover a free surface of the traces. The circuit die can also be surrounded by a curing product of a second polymer liquid.

Thin semiconductor chip using a dummy sidewall layer

The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 μm in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.

Flexible circuit board and heat spreader thereof

A flexible circuit board includes a flexible substrate, an electronic component and a heat spreader. The electronic component and the heat spreader are disposed on a top surface and a bottom surface of the flexible substrate, respectively. The heat spreader includes a copper layer which contains more than or equal to 50% copper grains by volume with (1,0,0) crystallographic orientation.

FLEXIBLE PASSIVE ELECTRONIC COMPONENT AND METHOD FOR PRODUCING THE SAME

A flexible passive electronic component includes a substrate, which comprises an insulating layer and optionally an inorganic layer with an upper side and a lower side, whereby the insulating layer at least partially covers the upper side of the optional inorganic layer. The flexible passive electronic component further comprises an electrical structure at least partially covering the insulating layer. The substrate has a thickness, which is at most 500 μm. The flexible passive electronic component has a height, which is at most 150 11 μm.

Waferscale physiological characteristic sensor package with integrated wireless transmitter

An embodiment of a sensor device includes a base substrate, a circuit pattern formed overlying the interior surface of the substrate, a physiological characteristic sensor element on the exterior surface of the substrate, conductive plug elements located in vias formed through the substrate, each conductive plug element having one end coupled to a sensor electrode, and having another end coupled to the circuit pattern, a multilayer component stack carried on the substrate and connected to the circuit pattern, the stack including features and components to provide processing and wireless communication functionality for sensor data obtained in association with operation of the sensor device, and an enclosure structure coupled to the substrate to enclose the interior surface of the substrate, the circuit pattern, and the stack.