Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

A chip package includes a semiconductor substrate, an interlayer dielectric (ILD) layer, a first metal shielding layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, an inclined sidewall adjoining the first and second surfaces, and a through hole through the first and second surfaces. The ILD layer is located on the first surface of the semiconductor substrate, and a first conductive pad structure and a second conductive pad structure are disposed in the ILD layer. The first metal shielding layer is located on the ILD layer. A portion of the first metal shielding layer is located in the ILD layer and on the second conductive pad structure. The redistribution layer is located on the second surface of the semiconductor substrate, a wall surface of the through hole, and the first conductive pad structure.

An integrated device package is disclosed. The integrated device package can include an antenna structure and an integrated device die electrically coupled to the antenna structure. The antenna structure can be formed with a system board or separated from the system board. When the antenna structure is formed with the system board, the integrated device package can include a redistribution layer having conductive routing traces such that the integrated device die is disposed between the system board and the redistribution layer, and the integrated device die is electrically coupled to the antenna structure at least partially through one or more of the conductive routing traces of the redistribution layer. When the antenna structure is separated from the system board, the integrated device die can be positioned between the antenna structure and the system board, and the integrated device die can be electrically coupled to the antenna structure at least partially through one or more of conductive routing traces of the system board and conductive wire of an interconnect structure between the system board and the antenna structure.

A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path.

Micro-isolators exhibiting enhanced isolation breakdown voltage are described. The micro-isolators may include an electrically floating ring surrounding one of the isolator elements of the micro-isolator. The isolator elements may be capacitor plates or coils. The electrically floating ring surrounding one of the isolator elements may reduce the electric field at the outer edge of the isolator element, thereby enhancing the isolation breakdown voltage.

An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.

A three-dimensional device structure includes a first die, a second die disposed on the first die, and a connection circuit. The first die includes a first semiconductor substrate, a first interconnect structure disposed on the first semiconductor substrate, and a first seal surrounding the interconnect structure. The second die includes a second semiconductor substrate, a second interconnect structure disposed on the second semiconductor substrate, and a second seal ring surrounding the interconnect structure. The first connection circuit electrically couples the first seal ring to the second seal ring to provide an electrostatic discharge path.

A circuit structure includes a substrate that includes a first transistor stack over the substrate that includes: a first transistor where the first transistor is a first conductivity type; and a second transistor, above the first transistor, where the second transistor is a second conductivity type different from the first conductivity type. The structure also includes a plurality of first conductive lines in a first metal layer above the first transistor stack, the plurality of first conductive lines electrically connected to the first transistor stack. The structure also includes a plurality of second conductive lines in a second metal layer below the substrate and underneath the first transistor stack, the plurality of second conductive lines electrically connected to the first transistor stack. The plurality of first conductive lines are configured asymmetrically with respect to the plurality of second conductive lines.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.

A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.