A fuse element includes a metal layer disposed on a substrate. The metal layer includes an intermediate segment, a first block and a second block. The first block and the second block are electrically connected to two respective ends of the intermediate segment. The fuse element also includes a dielectric layer covering the intermediate segment, the first block and the second block, a first passivation layer disposed on the dielectric layer, and a second passivation layer disposed on the first passivation layer. The fuse element further includes an opening penetrating through the first passivation layer, the second passivation layer and a portion of the dielectric layer, and located above the intermediate segment. In addition, a protective film is disposed on a bottom and a portion of a sidewall of the opening, and covers the first passivation layer exposed by the opening.

A semiconductor device, overvoltage detection structure is described that includes a current path including a Zener diode connected in series with a fuse. The Zener diode is configured to conduct a current in response to an overvoltage condition at a semiconductor device and the fuse is configured to permanently break the current path of the overvoltage detection structure in response to the Zener diode conducting the current.

A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

The present application provides a memory device. The memory device includes a semiconductor substrate including an isolation structure and an active area surrounded by the isolation structure; a fuse gate structure disposed over the active area; a device gate structure disposed over the active area and adjacent to the fuse gate structure; and a contact plug coupled to the active area and extending away from the semiconductor substrate, wherein at least a portion of the active area is disposed under the device gate structure. Further, a method of manufacturing the memory device is also disclosed.

A test structure for a semiconductor device, comprising a device under test including a transistor, the transistor having a gate electrode, a source electrode, a drain electrode and a bulk electrode, a first fuse and a second fuse provided in series, wherein one terminal of the first fuse is connected to the gate electrode, one terminal of the second fuse is connected to the bulk electrode, the other terminal of the first fuse and the other terminal of the second fuse being connected to each other, a first input/output pad connected to the first terminal of the first fuse and to the gate electrode of the transistor, a second input/output pad connected to the first terminal of the second fuse and to the bulk electrode of the transistor, a third input/output pad connected to the second terminal of the first fuse and the second terminal of the second fuse.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, an electrical overstress monitor and/or protection device includes a two different conductive structures configured to electrically arc in response to an EOS event and a sensing circuit configured to detect a change in a physical property of the two conductive structures caused by the EOS event. The two conductive structures have facing surfaces that have different shapes.

A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.

Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

An advanced e-Fuse structure is described. An e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure.