On-chip, doped semiconductor fuse regions compatible with FinFET CMOS fabrication are formed from the channel regions of selected fins. One or more fin dimensions are optionally reduced in selected channel regions of the fins following dummy gate removal, such as height and/or width. The channel regions from which the fuse regions are formed are doped to provide electrical conductivity, amorphized using ion implantation, and then annealed to form substantially polycrystalline fuse regions. Source/drain regions function as terminals for the fuse regions.

Provided is a semiconductor device in which a fuse element, which is cuttable by a laser, can be stably cut. The fuse element includes an upper fuse element, a lower fuse wiring line, and a fuse connecting contact such that, in cutting the fuse element by a laser, the lower fuse wiring line is protected by an inter-layer film, and only the upper fuse element is efficiently melted and evaporated. In addition, the contact for connecting the upper fuse element and the lower fuse wiring line to each other is formed at a center of a laser irradiation region, and hence the connection portion receives the energy of the laser most efficiently.

A secure demand paging system includes a secure internal memory having a table relating physical addresses to virtual addresses, a non-volatile memory, a decryption module and a hash module between the secure memory and the non-volatile memory to allow for decryption and integrity verification of data stored in the non-volatile memory during a transfer to said secure memory and means for connecting the secure memory to a volatile page swap memory such that the non-volatile memory is bypassable during a page swap.

A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on the wafer to obtain an altered wafer that has at least one selected portion altered. The method includes forming a structural layer over the altered wafer.

A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one of the plurality of semiconductor device structures. Based on a test result, a substance is provided on a selected portion of the wafer to selectively configure a circuit element within the at least one of the plurality of semiconductor device structures.

A method for use in manufacturing a plurality of electronic devices from a workpiece. The method includes compiling a set of data records in a data file, wherein each data record represents information uniquely associated with a respective electronic device to be manufactured from the workpiece. Based on the data file, deposition of a substance is controlled at selected locations on the workpiece.

A fuse device having contacts configured to reduce electro-migration is disclosed. In some exemplary embodiments, the fuse structure includes an anode disposed at a first end and a cathode disposed at a second end. A fuse link extends between and contacts the anode and the cathode. A boundary between the fuse link and the cathode has a center point, and each connector of a plurality of cathode connectors has a center point that is an equal distance from the center point of the boundary between the fuse link and the cathode. In some such embodiments, each connector of the plurality of cathode connectors is a different size than an anode connector, whereas in some such embodiments, each connector of the plurality of cathode connectors is substantially a same size as the anode connector along at least one axis.

A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

A semiconductor structure including a stacked FinFET fuse is provided in which the stacked FinFET fuse includes a plurality of vertically stacked and spaced apart conductive semiconductor fin portions and a doped epitaxial semiconductor material structure located on exposed surfaces of each conductive semiconductor fin portion of the vertical stack. In the FinFET fuse, a topmost surface of a bottom doped epitaxial semiconductor material structure is merged to a bottommost surface of an overlying doped epitaxial semiconductor material structure.

A plurality of semiconductor devices are arranged in a stack. Individual semiconductor devices within the stack are selected by an identity signal sent into the stack. The signal is compared within each stack to a unique stack identifier stored within each of the semiconductor devices and, when the signal is the same as the unique stack identifier, the semiconductor device is selected while, when the signal is not the same as the unique stack identifier, the semiconductor device remains within the default bypass mode.