An adjustment method for the chip output characteristics can include the following steps. When adjusting the output characteristics of the chip to be tested, first it is determined whether the output characteristics of the chip to be tested have been adjusted according to the state of each E-fuse. When determining that the output characteristics of the chip to be tested have not been adjusted, the target adjustment solution corresponding to the chip is determined among a plurality of adjustment solutions in a targeted manner according to the output performance of the chip to be tested. The E-fuse in the chip to be tested is subjected to blowing treatment according to the target adjustment solution, so as to adjust the output characteristics of the chip to be tested.

Disclosed are an integrated circuit device and a formation method thereof. The formation method of an integrated circuit device comprises the following steps: providing a substrate, wherein a first plug and a second plug are disposed inside the substrate; forming a first covering layer covering the substrate; forming, in the first region, a first opening exposing the first plug; forming a first conductive layer in the first opening; forming an isolation layer covering the first conductive layer and the first covering layer; forming, in the first region, a contact hole exposing the first conductive layer and a trench located above the contact hole and connecting with the contact hole, and forming, in the second region, a second opening exposing the second plug; and forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse wire in the second opening.

A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.

The present disclosure relates to semiconductor structures and, more particularly, to electronic fuse (e-fuse) cells integrated with a bipolar device and methods of manufacture. The structure includes: a bipolar device comprising a collector region, a base region and an emitter region; and an e-fuse integrated with and extending from the emitter region of the bipolar device.

A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer includes a second die arranged adjacent to the first die. The second die includes a second integrated circuit and at least one contact pad arranged to allow an electrical connection to be made to the second integrated circuit. The at least one contact pad is additionally electrically connected to the at least one trimmable or programmable component of the first die such that the at least one contact pad of the second die is configured to act as a probe pad.

The present disclosure relates to a semiconductor device, a solid-state imaging device, and a method for manufacturing a semiconductor device capable of improving the voltage dependency of a gate capacitance type.

Provided is a semiconductor device having a laminated structure in which a compound layer formed on a surface of a semiconductor layer and formed by the semiconductor layer reacting with metal, an insulating film layer in contact with the compound layer, and an electrode layer formed on the insulating film layer are laminated. The present technology can be applied, for example, to an analog-to-digital (AD) conversion part included in the solid-state imaging device.

A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

A memory device and a manufacturing method thereof are provided. The memory device includes a transistor, a first embedded insulating structure and a second embedded insulating structure. The transistor is formed on a substrate, and includes a gate structure, channel structures, a source electrode and a drain electrode. The channel structures penetrate through the gate structure, and are in contact with the source and drain electrodes. The first and second embedded insulating structures are disposed in the substrate, and overlapped with the source and drain electrodes. The first and second embedded insulating structures are laterally spaced apart from each other by a portion of the substrate lying under the gate structure.

An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

A semiconductor layout structure includes a substrate, a plurality of gate structures, and a plurality of conductive structures. The substrate includes a plurality of active regions extending along a first direction, in which the active regions are separated from each other by an isolation structure. The transistors are respectively disposed in the active regions. The gate structures extend across the active regions along a second direction that is perpendicular to the first direction, in which each of the active regions includes a pair of source/drain portions at opposite sides of each of the gate structures. The conductive structures are embedded in a first portion of the isolation structure disposed between the adjacent active regions in the first direction, wherein the conductive structures extend along the second direction and are separated from the source/drain portions by the isolation structure.