A power component includes two electric terminals, a component housing, a main component at least partially surrounded by the component housing, connected with the two terminals, and configured to carry a power current flowing between the two electric terminals, and a sensor and emitter unit which is configured to measure a value of a physical quantity (T, V, ΔV) characterizing an operating state of the main component, and to emit an electromagnetic signal, in which the measured value of the physical quantity is encoded. The sensor and emitter unit includes an antenna for emitting the electromagnetic signal which is spaced apart from the main component and arranged in, on and/or at the component housing.

A semiconductor structure includes a substrate, first and second transistors, first and second fuses, a contact structure, and a dielectric layer. The substrate has first and second device regions, and a fuse region. The first and second transistors are respectively above the first and second device regions. The first fuse is electrically connected to the first transistor and includes a first fuse active region having first and second portions. The second fuse is electrically connected to the second transistor and includes a second fuse active region having third and fourth portions. The contact structure interconnects the second portion and the third portion, wherein the first portion and the fourth portion are on opposite sides of the contact structure. The dielectric layer is between the contact structure and the fuse region of the substrate.

An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.

An electronic device includes: a control terminal, which extends on a first face of a substrate; a first conduction terminal, which extends in the substrate at the first face of the substrate; a first insulating layer interposed between the control terminal and the first conduction terminal; a conductive path, which can be biased at a biasing voltage; and a protection element, coupled to the control terminal and to the conductive path, which forms an electrical connection between the control terminal and the conductive path and is designed to melt, and thus interrupt electrical connection, in the presence of a leakage current higher than a critical threshold between the control terminal and the first conduction terminal through the first insulating layer.

The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.

A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.

An integrated circuit includes a first region corresponding to a first circuit and including a first dummy pattern and a first signal pattern which are spaced apart from each other by a width of a spacer in a conductive layer to extend in parallel in a first horizontal direction and a second region corresponding to a second circuit which is the same as the first circuit and including a second dummy pattern and a second signal pattern which are spaced apart from each other by the width of the spacer in the conductive layer to extend in parallel in the first horizontal direction. The first signal pattern and the second signal pattern are configured so that a first signal and a second signal corresponding to each other in the first circuit and the second circuit are respectively applied to the first signal pattern and the second signal pattern.

A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.

An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.