A surface-mountable thin-film fuse component is disclosed that may include a substrate having a top surface, a first end, and a second end that is spaced apart from the first end in a longitudinal direction. The thin-film component may include a fuse layer formed over the top surface of the substrate. The fuse layer may include a thin-film fuse track. An external terminal may be disposed along the first end of the substrate and electrically connected with the thin-film fuse track. The external terminal may include a compliant layer comprising a conductive polymeric composition.

Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.

A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without conductive failure or breakdown. The conductor has a width less than the threshold. When an electrostatic discharge event occurs, if the current exceeds a critical amount of current, the conductor experiences conductive breakdown and current ceases to flow. During later testing, this series path is tested for open connections, which indicate whether the conductor acting as an electrical on-die fuse experienced conductive failure during assembly of a semiconductor chip.

A device includes an electrical circuit having a first set of circuit elements. The device further includes a first set of conductive pillars over a first side of a substrate. The device further includes a first conductive rail electrically connected to each of the first set of conductive pillars, wherein each of the first set of conductive pillars is electrically connected to each of the first set of circuit elements by the first conductive rail. The device further includes a first plurality of power pillars extending through the substrate, wherein each of the first plurality of power pillars is electrically connected to the first conductive rail.

A semiconductor integrated circuit device (1000) includes: a first semiconductor chip CHP1 having a first circuit; and a second semiconductor chip (CHP2) having a second circuit and differing from the first semiconductor chip (CHP1). The semiconductor integrated circuit device (1000) further includes a control circuit (BTCNT) for controlling an operation of the first circuit and an operation of the second circuit in accordance with a control signal in a burn-in test, and the control circuit (BTCNT) controls the first circuit and the second circuit such that an amount of stress applied to the first semiconductor chip (CHP1) due to an operation of the first circuit and an amount of stress applied to the second semiconductor chip (CHP2) due to an operation of the second circuit differ from each other in the burn-in test.

A reading circuit for a die ID in a chip is provided. The reading circuit includes a chip damage detection circuit, a switch selector, a fuse controller, and a fuse device, where the fuse device stores the die ID; the fuse controller reads the die ID from the fuse device; the chip damage detection circuit detects whether a processor in the chip is capable of operating properly, so as to obtain a detection result, and notify the switch selector of the detection result; and when the detection result is that the processor is capable of operating properly, the switch selector connects the processor and the fuse controller; and when the detection result is that the processor is not capable of operating properly, the switch selector connects the fuse controller and a maintenance device that is located outside the chip.

A method for use in manufacturing semiconductor devices includes providing a structured layer on a wafer, and selectively providing a substance on a selected portion of the structured layer. A die comprises a semiconductor device on a substrate, where the semiconductor device includes a substance, and where the substance has a sidewall that is sheer with respect to one or more of a base surface or a top surface of the substrate.

The disclosure discloses a layout structure of an eFuse unit, comprising pad, link, and shield, wherein: a pad is respectively disposed on both ends of the link in a length direction; the shield and the link are at the same metal layer; the shield comprises a plurality of independent metal wires; the plurality of independent metal wires are arranged on both sides of the link; the length of each independent metal wire is greater than the width thereof; and a length direction of each independent metal wire is perpendicular to the length direction of the link. The disclosure not only forms a barrier protection layer for preventing burst metal spraying from affecting other circuits, but also can prevent spayed metal from reflecting back and connecting to a broken link, so as to improve the programming reliability of the eFuse unit.

A method for preparing a reference transistor test structure having a transistor with multiple terminals is provided. The method may include placing a set of bond pads at a first layer of the reference transistor test structure with each of the bond pads connecting to its corresponding terminal of the transistor, wherein the first layer of the reference transistor test structure is an uppermost metal layer. The method may further include placing a first protection device at a second layer of the reference transistor test structure and connecting the first protection device to at least one of the terminals of the transistor, wherein the second layer is a lowermost metal layer.

Semiconductor fuses and methods of forming the same include forming a dummy gate on a semiconductor fin. A dielectric layer is formed around the dummy gate. The dummy gate is removed to expose a region of the semiconductor fin. The exposed region is metallized.