A stacked-die image sensor may be provided with an array of image pixels. The stacked-die image sensor may include at least first and second integrated circuit dies stacked on top of one another. Some of the pixel circuitry in each pixel may be formed in the first integrated circuit die and some of the pixel circuitry in each pixel may be formed in the second integrated circuit die. Coupling structures such as conductive pads may electrically couple the pixel circuitry in the first integrated circuit die to the pixel circuitry in the second integrated circuit die. A shielding structure may partially or completely surround each conductive pad to reduce parasitic capacitive coupling between adjacent conductive pads. The shielding structure may be a metal wire coupled to a ground voltage. The shielding structure may extend between columns of image pixels and/or between rows of image pixels.

A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

A semiconductor device is disclosed. The semiconductor device includes: a first die including a signal pad region and a power pad region; a redistribution layer (RDL) over the first die; a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die; a plurality of second connectors over the RDL and at the side opposite to the first die; a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die so as to correspond the signal pad region of the first die to the signal pad region of the second die. An associated method for fabricating the same is also disclosed.

A rectifier package is provided, which comprises a first rectifier die having an anode and a cathode conductively bonded to a first conductive film on a first surface. The rectifier package also comprises a second rectifier die having an anode and a cathode conductively bonded to the first conductive film on a second surface, which is opposite to the first surface. The first conductive film is in contact with both anodes or both cathodes of the first rectifier die and the second rectifier die.

In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes an image sensor disposed within a first substrate. A first band-pass filter and a second band-pass filter are disposed on the first substrate. A dielectric structure is disposed on the first substrate. The dielectric structure is laterally between the first band-pass filter and the second band-pass filter and laterally abuts the first band-pass filter and the second band-pass filter.

A method for producing a multiple-substrate stack from an, in particular wavelength-sensitive, semiconductor substrate and at least one further, in particular wavelength-sensitive, semiconductor substrate with the following steps: applying a dielectric layer, which is electrically conductive at least in certain sections, onto at least one substrate surface of at least one of the semiconductor substrates, and contacting the semiconductor substrate with the further semiconductor substrate and forming an electrically conductive connection between the semiconductor substrates.

The present disclosure provides a method for preparing a semiconductor package structure. The method includes the following steps. A first die is provided. A second die including a plurality of first conductors is bonded to the first die. A plurality of second conductors are disposed on the first die. A molding is disposed to encapsulate the first die, the second die and the plurality of second conductors. An RDL is disposed on the second die and the molding. A plurality of connecting structures are disposed on the RDL.

The present technology relates to a solid-state imaging device, a manufacturing method thereof, and an electronic device that enable improvement of the sensitivity in a near infrared region by a simpler process. A solid-state imaging device includes: a first semiconductor layer in which a first photoelectric conversion unit and a first floating diffusion are formed; a second semiconductor layer in which a second photoelectric conversion unit and a second floating diffusion are formed; and a wiring layer including a wiring electrically connected to the first and second floating diffusions. The first semiconductor layer and the second semiconductor layer are laminated, and the wiring layer is formed on a side of the first or second semiconductor layer, the side being opposite to a side on which the first semiconductor layer and the second semiconductor layer face each other. The present technology can be applied to a CMOS image sensor.

A solar cell of an embodiment includes: a transparent substrate; a p-electrode on the substrate, the p-electrode including a first p-electrode containing an Sn-based metal oxide, a second p-electrode having an opening and consisting of a wiring containing a metal or graphene, and a third p-electrode containing an In-based metal oxide; a p-type light absorbing layer in direct contact with a surface of the first p-electrode on a side opposite to the second p-electrode side; an n-type layer provided on the p-type light absorbing layer; and an n-electrode provided on the n-type layer. The third p-electrode is provided to be present between the first p-electrode and the second p-electrode and to be in direct contact with an upper surface of the second p-electrode. An entire side surface of the second p-electrode is in direct contact with the first p-electrode.

According to one embodiment, a multi-junction solar cell includes a first solar cell, a second solar cell, and an insulating layer. The first solar cell includes a first photoelectric conversion element. The second solar cell is connected in parallel with the first solar cell. The second solar cell includes multiple second photoelectric conversion elements connected in series. The insulating layer is provided between the first solar cell and the second solar cell. The second photoelectric conversion element includes a p-electrode and an n-electrode. The p-electrode is connected to a p.sup.+-region including a surface on a side opposite to a light incident surface. The n-electrode is connected to an n.sup.+-region including the surface on the side opposite to the light incident surface. The p-electrodes oppose each other or the n-electrodes oppose each other in a region where the multiple second photoelectric conversion elements are adjacent to each other.