A semiconductor device includes transistor cells in a semiconductor portion, wherein the transistor cells are electrically connected to a gate metallization, a source electrode and a drain electrode. In one example, the semiconductor device further includes a doped region in the semiconductor portion. The doped region is electrically connected to the source electrode. A resistance of the doped region has a negative temperature coefficient. An interlayer dielectric separates the gate metallization from the doped region. A drain structure in the semiconductor portion electrically connects the transistor cells with the drain electrode and forms a pn junction with the doped region.

A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

A thermal control circuit is described. The thermal control circuit includes a heating element disposed within an electronic circuit board having a semiconductor chip disposed thereon. The thermal control circuit includes a power management integrated circuit coupled to the heating element. The power management integrated circuit is to enable the heating element to heat the semiconductor chip at least to the semiconductor chips' lowest rated operating temperature prior to the semiconductor chip being placed in a fully operational state.

The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.

A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.

A thermoelectric module includes a plurality of thermoelectric components, a first electrode and a second electrode. The thermoelectric components have the same type of semiconductor material. The first electrode includes a first parallel connection part and a first serial connection part. The plurality of thermoelectric components is electrically connected to the first parallel connection part and each of the plurality of thermoelectric components is separated from one another. The first serial connection part is configured for being electrically connected to other electrical components. The plurality of thermoelectric components is electrically connected to the second electrode and located between the first parallel connection part and the second electrode.

A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

A semiconductor device is provided that includes a temperature sensing function that accurately senses a temperature. The semiconductor device includes a first semiconductor layer on a semiconductor substrate, and a temperature sensor. The temperature sensor includes: a sensing-body region of a second conductivity type that is disposed in the first semiconductor layer; a first region of a first conductivity type, and a second region of the first conductivity type that are arranged in the sensing-body region and are apart from each other; and a third region of the second conductivity type that is in the sensing-body region and is between the first region and the second region. A concentration of a first conductivity type impurity in the temperature-sensing conductive layer is higher than a concentration of a first conductivity type impurity in the drift region.

A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.

This invention aims at providing a temperature characteristic adjustment circuit capable of adjusting the temperature characteristic to various positive and negative temperature characteristics with an excessively small characteristic variation and capable of suppressing an increase in the chip area and the current consumption with a simple circuit configuration. A temperature characteristic adjustment circuit has a current source having a nonvolatile storage element having a control gate region and a source region and driven by the application of a bias between the control gate region and the source region and an output circuit not having a nonvolatile storage element, in which the temperature dependency of an output signal originating from the temperature dependency of the current amount of a current output from the current source is adjusted by the nonvolatile storage element.