Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.

A display panel including a first current source and a first pixel unit is provided. The first pixel unit includes a first switch and a first light-emitting diode. The first switch is coupled to the first current source and receives a first scan signal. When the first scan signal is enabled, the first switch is turned on and receives a first current provided by the first current source. The first light-emitting diode is coupled to the first switch. When the first switch is turned on, the first current passes through the first light-emitting diode to turn on the first light-emitting diode.

An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.

According to one embodiment, a semiconductor device includes: a potential supply terminal to which a potential is supplied; a terminal (I/O terminal) for exchanging a signal with an outside; an I/O current detection load circuit electrically connected to the potential supply terminal and the terminal; and a current sensor circuit detecting the I/O current flowing through the I/O current detection load circuit. The current sensor circuit acquires a sensor current proportional to the I/O current and outputs the acquired sensor current as output information, and the I/O current is an abnormal current flowing through the I/O terminal due to at least one of electrostatic discharge and electromagnetic susceptibility and is a current that is greater than a predetermined current and that causes an abnormal state.

Embodiments of the present disclosure provide a display panel and a display device, the display panel includes: a base substrate; a plurality of light emitting devices on the base substrate; an encapsulation layer covering the light emitting devices; a mirror layer located on a side of the encapsulation layer away from the base substrate, the mirror layer including a plurality of first openings, and an orthographic projection of each first opening on the base substrate overlapping an orthographic projection of at least one light emitting device on the base substrate; a transparent filling layer located on a side of the encapsulation layer away from the base substrate, at least part of the transparent filling layer being located in the first openings.

The present disclosure relates to a device comprising a first transistor and a first circuit comprising first and second terminals, the first circuit being configured to generate a first voltage representing the temperature of the first transistor, a first terminal of the first circuit being coupled to the drain of the first transistor.

In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.

A programmable multi-band receiver includes a signal coupler, programmable signal scaler including a fixed capacitance part including a series set of switchable capacitor arrays positioned before Electrostatic Discharge (ESD) protecting circuitry coupled to a variable capacitance part after the ESD protecting circuitry, reconfigurable mixer array, then a baseband polyphase filter. The variable capacitance part includes a parallel set of paths each including a capacitor and at least one switch for setting a center frequency for band selection. The reconfigurable mixer array is coupled to receive phase signals from a local oscillator (LO) circuit and includes a plurality of mixer switch elements for providing image rejection. The received signal strength is adjusted by the programmable signal scaler so that the electrostatic discharge circuit (ESD) can operate without the need of a negative supply voltage.