A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

Gallium nitride-based monolithic microwave integrated circuits (MMICs) can comprise aluminum-based metals. Electrical contacts for gates, sources, and drains of transistors can include aluminum-containing metallic materials. Additionally, connectors, inductors, and interconnect devices can also comprise aluminum-based metals. The gallium-based MMICs can be manufactured in complementary metal oxide semiconductor (CMOS) facilities with equipment that produces silicon-based semiconductor devices.

Methods and apparatus to form silicon-based transistors on group III-nitride materials using aspect ratio trapping are disclosed. An example integrated circuit includes a group III-nitride substrate and a fin of silicon formed on the group III-nitride substrate. The integrated circuit further includes a first transistor formed on the fin of silicon and a second transistor formed on the group III-nitride substrate.

Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.

A capacitor structure includes an insulation layer and a capacitor unit disposed on the insulation layer. The capacitor unit includes a first electrode, a second electrode, a first dielectric layer, and a patterned conductive layer. The second electrode is disposed above the first electrode in a vertical direction. The first dielectric layer is disposed between the first electrode and the second electrode in the vertical direction. The patterned conductive layer is disposed between first electrode and the second electrode, the patterned conductive layer is electrically connected with the first electrode, and the first dielectric layer surrounds the patterned conductive layer in a horizontal direction.

The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.

A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.