Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.

An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.

There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120)comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an Al.sub.yGa.sub.y-1N layer structure (380), wherein 0<y≤1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an Al.sub.xGa.sub.x-1N layer structure (389), wherein 0≤x<1, wherein the Al.sub.xGa.sub.x-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an Al processing system comprising said FPGA device (100).

A Compact CMOS System having a non-split Channel Regions Controlling Gate, including a material which forms rectifying junctions with both N and P-type Field Induced Semiconductor, and at least two Channels electrically connected thereto and projecting substantially away therefrom adjacent and parallel to one another. There further being substantially non-rectifying junctions to the material which forms a rectifying junction with both N and P-type Field Induced Semiconductor, and to distal ends of the at least two Channels.

Gallium nitride (GaN) epitaxy on patterned substrates for integrated circuit technology is described. In an example, an integrated circuit structure includes a material layer including gallium and nitrogen, the material layer having a first side and a second side opposite the first side. A plurality of fins is on the first side of the material layer, the plurality of fins including silicon. A device layer is on the second side of the material layer, the device layer including one or more GaN-based devices.

The disclosure concerns an electronic device provided with two high electron mobility transistors stacked on each other and having in common their source, drain, and gate electrodes. For example, each of these electrodes extends perpendicularly to the two transistors. For example, the source and drain electrodes electrically contact the conduction channels of each of the transistors so that said channels are electrically connected in parallel.

Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10.sup.17 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10.sup.17 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.