According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

A semiconductor device may include a first-type substrate. The semiconductor device may further include a second-type well configured to form a PN junction with the first-type substrate. The semiconductor device may further include a diode component configured to form a diode with the second-type well. The diode may be connected to the PN junction in a reverse series connection. The second-type may be N-type if the first-type is P-type, and wherein the second-type may be P-type if the first-type is N-type.

A device includes a dielectric layer, an interlayer metal pad in the dielectric layer, a first capacitor over the interlayer metal pad, and a second capacitor over the dielectric layer. The first capacitor includes a first bottom capacitor electrode over and in contact with the interlayer metal pad, a first top capacitor electrode, and a first inter-electrode dielectric layer between the first bottom capacitor electrode and the first top capacitor electrode. The second capacitor includes a second bottom capacitor electrode over and in contact with the dielectric layer, a second top capacitor electrode, and a second inter-electrode dielectric layer between the second bottom capacitor electrode and the second top capacitor electrode.

A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

Provided is a semiconductor device including a semiconductor substrate provided with a transistor portion, wherein the semiconductor substrate includes, in the transistor portion, a drift region of a first conductivity type; an accumulation region of the first conductivity type that has a higher doping concentration than the drift region; a collector region of a second conductivity type; and a plurality of gate trench portions and a plurality of dummy trench portions that are provided extending in a predetermined extension direction in the top surface of the semiconductor substrate, and are arranged in an arrangement direction orthogonal to the extension direction, and the transistor portion includes a first region that includes a gate trench portion; and a second region in which the number of dummy trench portions arranged in a unit length in the arrangement direction is greater than in the first region.

A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or source fingers (31) to each other in a region which is located outside an active region (11) and on a side where a drain pad (42) is disposed. The multi-finger transistor is configured to be linearly symmetric with respect to a direction of propagation of a signal from a gate pad (22) at the position of the gate pad (22).

Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a substrate and having channel, source, and drain regions. The method includes forming a well in the semiconductor layer to have a first dopant, and implanting a second dopant into the well. The first and second dopants are of opposite doping types. A first portion of the well has a higher concentration of the second dopant than the first dopant. A second portion of the well under the first portion has a higher concentration of the first dopant than the second dopant. The method further includes forming a gate stack over the channel region, and forming source and drain features in the source and drain regions. The first portion of the well electrically connects the source and drain features.

A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector active region, depositing a dielectric anti-reflective (DARC) layer over the collector dielectric layer, dry etching away a base opening in the DARC layer, and wet etching away a portion of the collector dielectric layer in the base opening to provide an extended base opening to the substrate. The method further comprises performing a base deposition to form a base epitaxy region in the extended base opening and extending over first and second portions of the DARC layer that remains as a result of the dry etching away the base opening in the DARC layer, and forming an emitter region over the base epitaxy region.

A semiconductor device of the present invention includes: an IGBT including an emitter layer on a first main surface side of a semiconductor substrate and a collector layer on a second main surface side of the semiconductor substrate; a freewheeling diode including an anode layer on the first main surface side of the semiconductor substrate and a cathode layer on the second main surface side of the semiconductor substrate; a well region that is located in a boundary between the IGBT and the freewheeling diode and separates the IGBT and the freewheeling diode; a first electrode located on the first main surface of the semiconductor substrate so as to be connected to the emitter layer, the anode layer, and the well region; a resistance element located between the well region and the first electrode.