Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

A semiconductor device includes a first-conductivity-type semiconductor substrate that has a first main surface on one side and a second main surface on another side, a second-conductivity-type well region that is formed in a surface layer portion of the first main surface and that demarcates an active region and an outer region in the semiconductor substrate, an IGBT including a second-conductivity-type collector region formed at the active region in a surface layer portion of the second main surface and an FET structure formed at the active region in the first main surface, and a diode that includes a first-conductivity-type cathode region formed only at the outer region in the surface layer portion of the second main surface and that has the well region serving as an anode region.

A semiconductor device includes: an FET structure that is formed next to a looped trench on a semiconductor substrate and that has an n.sup.+ emitter region and an n.sup.− drain region facing each other in the depth direction of the looped trench across a p-type base region; a p-type floating region formed on the side of the looped trench opposite to the FET structure; and an emitter connecting part that is electrically connected to the n.sup.+ emitter region and a trench gate provided in the same trench, the emitter connecting part and the trench gate being insulated from each other by the looped trench. The trench gate faces the FET structure, and the emitter connecting part faces the p-type floating region, across an insulating film.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.

A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

Provided is a semiconductor device including a semiconductor substrate having a transistor portion and a diode portion; and an emitter electrode and a gate electrode provided above a front surface of the semiconductor substrate, wherein the transistor portion has a plurality of trench portions electrically connected to the gate electrode, a drift region of a first conductivity type provided in the semiconductor substrate, a base region of a second conductivity type provided above the drift region, and a trench bottom barrier region of a second conductivity type provided between the drift region and the base region and having a higher doping concentration than that of the base region, and the trench bottom barrier region is electrically connected to the emitter electrode.

A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.

A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.

A semiconductor device including a semiconductor substrate, first and second transistor sections and a diode section provided on the substrate, is provided. The diode section is arranged to be adjacent to and sandwiched between the first and second transistor sections in a predetermined arrangement direction. The diode section includes a drift region; a base region above the drift region; first cathode regions and second cathode regions below the drift region. The first and second transistor sections each include a collector region. The first cathode regions are provided continuously between the collector regions of the first and second transistor sections. One end and another end of the first cathode regions in the arrangement direction are in contact with the collector regions of the first and second transistor sections, respectively. The first and second cathode regions are in contact with each other and alternating in a direction orthogonal to the arrangement direction.