A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first electrode electrically connected to the semiconductor base body; a first semiconductor region of a second conductivity-type provided at an upper part of the semiconductor base body; a second semiconductor region of the first conductivity-type provided at an upper part of the first semiconductor region; a second electrode electrically connected to the first semiconductor region; an insulating film provided on a top surface of the second semiconductor region; and a passive element provided on a top surface of the insulating film.

The present application provides a semiconductor die with decoupling capacitors and a manufacturing method of the semiconductor die. The semiconductor die includes first bonding pads, second bonding pads, bond metals and decoupling capacitors. The first bonding pads are coupled to a power supply voltage. The second bonding pads are coupled to a reference voltage. The bond metals are disposed on central portions of the first and second bonding pads. The decoupling capacitors are disposed under the first and second bonding pads, and overlapped with peripheral portions of the first and second bonding pads. The decoupling capacitors are in parallel connection with one another. First terminals of the decoupling capacitors are electrically connected to the first bonding pads, and second terminals of the decoupling capacitors are electrically connected to the second bonding pads.

According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface portion of the substrate, an oxide film formed on the substrate and having a first opening to selectively expose the impurity diffusion layer, a dielectric film formed on the impurity region having been exposed from the oxide film, and a first electrode opposed to the impurity diffusion layer with the dielectric film therebetween, wherein the impurity concentration on the front surface portion of the impurity diffusion layer is 5×10.sup.19 cm.sup.−3 or more.

An electronic device can include one or more trenches that include a material that defines one or more voids. In an embodiment, the substrate defines a first trench having a first portion and a second portion laterally adjacent to the first portion, wherein the first portion has with a first width, the second portion has a second width, and the first width is wider than the second width. The material defines a first void at a predetermined location within the first portion of the first trench and has a seam within the second portion of the first trench. In another embodiment, the substrate defining a trench, and the material that defines spaced-apart voids at predetermined locations within the trench. A process of forming the electronic device can include patterning a substrate to define a trench, and depositing a material within the trench, wherein the deposited material defines a void.

Various embodiments of the present application are directed towards a metal-insulator-metal (MIM) capacitor. The MIM capacitor comprises a bottom electrode disposed over a semiconductor substrate. A top electrode is disposed over and overlies the bottom electrode. A capacitor insulator structure is disposed between the bottom electrode and the top electrode. The capacitor insulator structure comprises at least three dielectric structures vertically stacked upon each other. A bottom half of the capacitor insulator structure is a mirror image of a top half of the capacitor insulator structure in terms of dielectric materials of the dielectric structures.

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

A high voltage metal-oxide-metal (HV-MOM) layout includes a first conductive element. The first element includes a first leg extending in a first direction, a second leg connected to the first leg, the second leg extending in a second direction different from the first direction, and a third leg connected to the second leg, the third leg extending in a first direction. The HV-MOM layout further includes a second conductive element separated from the first conductive element by a space. The second conductive element includes a serpentine structure, wherein the serpentine structure is enclosed on at least three sides by the first conductive element. The HV-MOM layout further includes a dielectric material filling the space between the first conductive element and the second conductive element.

A passive element package includes a first substrate, first passive elements disposed on the first substrate, a second substrate disposed on the first passive elements, second passive elements disposed on the second substrate, and a sealant that seals the first passive elements and the second passive elements. The passive element package can reduce the size of a semiconductor module that includes the passive element package.