An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.

A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m.sub.1, with m.sub.10.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m.sub.11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m.sub.12. The first partial junction grading coefficient m.sub.11 is different to the second partial junction grading coefficient m.sub.12, with m.sub.11m.sub.12. At least one of the first and second partial junction grading coefficients m.sub.11, m.sub.12 is greater than 0.50, with m.sub.11 and/or m.sub.12>0.50. The first junction grading coefficient m.sub.1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m.sub.11, m.sub.12.

According to one aspect of the present disclosure, a terahertz device is provided. The terahertz device includes a semiconductor substrate, a terahertz element, and a first rectifying element. The terahertz element is disposed on the semiconductor substrate. The first rectifying element is electrically connected to the terahertz element in parallel.

The present disclosure describes exemplary configurations and arrangements for various intelligent diodes. The intelligent diodes of the present disclosure can be implemented as part of electrostatic discharge protection circuitry to protect other electronic circuitry from the flow of electricity caused by electrostatic discharge events. The electrostatic discharge protection circuitry dissipates one or more unwanted transient signals which result from the electrostatic discharge event. In some situations, some carrier electrons and/or carrier holes can flow from intelligent diodes of the present disclosure into a semiconductor substrate. The exemplary configurations and arrangements described herein include various regions designed collect these carrier electrons and/or carrier holes to reduce the likelihood these carrier electrons and/or carrier holes cause latch-up of the other electronic circuitry.

A transient voltage suppression (TVS) device, may include: a substrate base formed in a substrate, the substrate base comprising a semiconductor of a first conductivity type; and an epitaxial layer, disposed on the substrate base, on a first side of the substrate, and comprising a semiconductor of a second conductivity type. The epitaxial layer may include: a first portion, the first portion having a first layer thickness; and a second portion, the second portion having a second layer thickness, less than the first layer thickness, wherein the first portion and the second portion are disposed on a first side of the substrate, and wherein the first portion is electrically isolated from the second portion.

A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

A semiconductor device includes n pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient m.sub.i. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m.sub.1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m.sub.2. The junction grading coefficients m.sub.1, m.sub.2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m.sub.1, m.sub.2 are 0.25.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.