Multi-trench semiconductor device and method of manufacture thereof

Abstract

A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.

Claims

1. A semiconductor device comprising: a semiconductor substrate and a semiconductor layer located on a first major surface of the semiconductor substrate; and at least one shallow trench comprising a base region and sidewall regions; at least one deep trench comprising a base region and sidewall regions, each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer, wherein the respective sidewall regions and base region of the respective at least one shallow trench and at least one deep trench each comprise a doped trench region and are at least partially filled with a conductive material contacting the doped trench region, wherein the at least one shallow trench terminates in the semiconductor layer and the at least one deep trench terminates in the semiconductor substrate; an isolating layer formed on the first major surface of the semiconductor layer directly above the at least one shallow trench and the at least one deep trench; and a first electrical contact formed on the isolating layer and electrically connected to the conductive material of either the at least one shallow trench or the at least one deep trench by a via through the isolating layer.

2. The semiconductor device of claim 1, further comprising an alternating structure of a plurality of the shallow trenches and a plurality of the deep trenches.

3. The semiconductor device of claim 1, further comprising a second electrical contact arranged on a second major surface of the semiconductor substrate opposing the first major surface of the semiconductor substrate.

4. The semiconductor device of claim 1, wherein the semiconductor substrate is a first conductivity type, the semiconductor layer is a second conductivity type, and the doped trench region is the first conductivity type.

5. The semiconductor device of claim 1, further comprising an additional isolating layer placed between the semiconductor substrate and the semiconductor layer.

6. A method of manufacturing a semiconductor device comprising: forming a semiconductor layer on a first major surface of a semiconductor substrate; forming an oxide on a first major surface of the semiconductor layer above regions where at least one shallow trench and at least one deep trench will be formed; forming windows in the oxide above the regions where the at least one shallow trench and at least one deep trench will be formed; forming a resist layer in the window where the at least one shallow trench will be formed; etching the region where the at least one deep trench is to be formed to a first depth by removing the semiconductor layer where no resist or oxide is present while simultaneously removing the resist layer in the region where the at least one shallow trench will be formed; forming the at least one deep trench and the at least one shallow trench by simultaneously etching the at least one deep trench and the at least one shallow trench to respective final depths so that each of the at least one shallow trench and at least one deep trench extends from the first major surface of the semiconductor layer, wherein the at least one shallow trench terminates in the semiconductor layer and the at least one deep trench terminates in the semiconductor substrate; forming a doped trench region at sidewall regions and a base region of the each of the at least one shallow trench and at least one deep trench; and forming a conductive material to contact the doped trench region in each of the at least one shallow trench and at least one deep trench.

7. The method of claim 6, comprising forming an alternating structure of a plurality of the shallow trenches and a plurality of the deep trenches.

8. The method of claim 6, further comprising forming a first electrical contact for electrically connecting to the conductive material of the at least one shallow trench.

9. The method of claim 8, further comprising forming a second electrical contact on a second major surface of the semiconductor substrate opposing the first major surface of the semiconductor substrate.

10. The method of claim 6, wherein forming the respective doped trench regions at the sidewall regions and base region of the at least one shallow trench and the at least one deep trench comprises exposing the respective sidewalls and base region of the respective at least one shallow trench and the at least one deep trench to a doping diffusion.

11. The method of claim 10, further comprising electrically contacting the conductive material of the at least one shallow trench to a common contact formed on the first major surface of the semiconductor layer.

12. The method of claim 11, further comprising electrically isolating the common contact formed on the first major surface of the semiconductor layer from the conductive material of the at least one deep trench.

Description

DESCRIPTION OF THE DRAWINGS

(1) The invention is described further hereinafter by way of example only with reference to the accompanying drawings in which:

(2) FIGS. 1A to 1D show steps in a method of manufacturing a semiconductor device in accordance with embodiments of the present disclosure;

(3) FIG. 2A shows a semiconductor device and associated current paths during operation in accordance with embodiments of the present disclosure;

(4) FIG. 2B shows back-to-back diodes characterising the semiconductor device in accordance with embodiments of the present disclosure;

(5) FIG. 2C shows a parallel network of diodes characterising the semiconductor device in accordance with embodiments of the present disclosure;

(6) FIG. 3 shows a semiconductor device in accordance with an embodiment of the present disclosure; and

(7) FIG. 4 shows a semiconductor device in accordance with an embodiment of the present disclosure.

(8) FIG. 5 shows a process for forming a semiconductor device in accordance with an embodiment of the present disclosure.

(9) In the figures and the following description and unless otherwise stated like reference numerals refer to like features.

(10) FIGS. 1A to 1D illustrate the principle process steps in an example method of manufacturing a semiconductor device 100 in accordance with embodiments of the present disclosure. As illustrated in FIG. 1A a semiconductor wafer 102 is provided. The semiconductor wafer 102 may comprise a semiconductor substrate 104 and a semiconductor layer 106 may be formed on the semiconductor substrate 104. The semiconductor layer 106 may be formed on the semiconductor substrate 104 by any appropriate process. For example, the semiconductor layer 106 may be formed by epitaxial techniques, diffusion, bonding or implantation. The semiconductor substrate 104 may be a silicon substrate.

(11) The semiconductor substrate 104 may be more highly doped than the semiconductor layer 106 and in this regard the semiconductor substrate 104 may be doped in the region 1e18 cm.sup.3 to 1e20 cm.sup.3 and the semiconductor layer 106 may be doped in the region 1e14 cm.sup.3 to 1e17 cm.sup.3. The semiconductor substrate 104 may be degenerately doped when compared to the semiconductor layer 106. In this way, the semiconductor substrate 104 may be considered to have low electrical resistance or in other words the semiconductor substrate 104 may be considered to be low ohmic.

(12) The conductivity type of the semiconductor substrate 104 may be opposite to the conductivity type of the semiconductor layer 106. For example, the semiconductor layer 106 may p-type and the semiconductor substrate 104 may be n-type.

(13) As illustrated in FIG. 1A, an alternating system of trenches 108a, 108b are formed in the wafer 102. The trenches 108a, 108b may be formed by lithographic techniques, laser etching or any appropriate semiconductor etching technique. The trenches 108a, 108b may extend from a first major surface 110 of the wafer 102 into the wafer 102.

(14) In FIG. 1A, an arrangement of deep trench 108a followed by shallow trench 108b may be repeated dependent on the level of surge protection required to form the alternating arrangement of trenches. The skilled person will appreciate that the arrangement of trenches may be such that there is one deep trench and one shallow trench. However, the skilled person will also appreciate that the greater number of shallow and deep trenches the larger the semiconductor junction area which in turn results in greater current carrying capabilities. The arrangement of trenches may begin with a deep or shallow trench and end with a deep or shallow trench. In other words, there is only a need for at least one deep and one shallow trench and the number of deep trenches need not equal the number of shallow trenches.

(15) The deep trenches 108a may be formed in the wafer 102 to extend into and through the semiconductor layer 106 and terminate in the semiconductor substrate 104. In other words, the depth of the deep trenches 108a should be deeper than the thickness of the semiconductor layer 106. The shallow trenches 108b may be formed in the wafer to extend into and terminate in the semiconductor layer 106. In other words, the depth of the shallow trenches should be shallower than the thickness of the semiconductor layer 106 such that the shallow trenches are not in physical contact with the semiconductor substrate 104. The distance between the bottom of the shallow trench 108b and the semiconductor substrate 104 may optionally be greater than the distance between the shallow trench 108b and the deep trench 108a.

(16) As mentioned, the trenches 108a, 108b may be formed by any appropriate etch process. By way of example (and not illustrated), to form trenches 108a, 108b of different depths in a single etch process, a protective oxide may be formed on the first major surface 110 of the wafer 102. The protective oxide may be formed thicker above the regions where the shallow trenches 108b are formed and the protective oxide may be formed thinner above the regions where the deep trenches 108b are formed.

(17) As shown in FIG. 5, at block 201 the protective oxide may, alternatively, only be formed in the regions where no trenches will be formed, thus as shown at block 202 defining processing openings or windows for subsequent processing of both the deep and shallow trenches 108a, 108b. At block 203, a resist layer may then be applied in the windows where the shallow trenches 108b will be formed. The area above the location where the shallow trenches are to be formed will be covered by the resist.

(18) At block 204, partial formation of the deep trenches 108a may begin by removing the silicon at areas where no resist or oxide is present, using for example dry etching processes such as a deep reactive ion etch. At block 205, during partial etching of the deep trench the resist is also removed. As a result, at block 206 the windows in the oxide openings of the shallow trenches will be accessible allowing the etch process to form the final trench shallow trench depth. In this way both the deep and shallow trenches may be etched simultaneously.

(19) Turning now to FIG. 1B, the side walls and the bottoms (also known as the base) of the trenches 108a, 108b are exposed to a doping atmosphere by heating and then exposing the side walls and the bottoms of the trenches 108a, 108b with a gas containing doping atoms. The doping atoms then diffuse into the silicon such that the side wall regions and base regions of the trenches 108a, 108b are doped to form respective diffusion layers 112 around each of the trenches. In this way diffusion layers 112 may be seen to encase each the trenches 108a, 108b. The diffusion layers 112 may be the same conductivity type as the semiconductor substrate 104. The diffusion layers 112 may be doped to the same or similar level as the semiconductor substrate 104, that is, in the region 1e18 cm.sup.3 to 1e20 cm.sup.3 for example.

(20) Following formation of the diffusion layers 112, each of the trenches 108a, 108b are filled with an electrically conductive material 114 as illustrated in FIG. 1C. The electrically conductive material 114 of each trench may form an ohmic contact with the diffusion layers 112 of the respective trench. The electrically conductive material may be doped poly-silicon or a suitable metal stack, formed of for example one or more of Cu, Ti or W.

(21) The next step of the method of manufacture is illustrated in FIG. 1D. The electrically conductive material 114 formed in each of the shallow trenches 108b is electrically connected to a common contact 116 formed on the first major surface 110 of the wafer 102. Conversely, the conductive material 114 formed in the deep trenches 108a is electrically isolated from the conductive material 114 of each of the shallow trenches and the common contact 116. The common contact 116 may be electrically isolated from the conductive material 114 formed in the deep trenches 108a by an appropriate isolating layer 118 such as oxide, nitride, oxynitride or an organic layer such as a Polyimide or a Polybenzoxazole. The isolating layer may be formed on the first major surface 110 of the wafer 102 prior to formation of the common contact 116. As required, through metal vias 120 or other suitable electrical connections may be made from the common contact 116 through the isolating layer 118 to the conductive material 114 formed in each of the shallow trenches 108b. Alternatively, the skilled person will understand that the deep trenches may be electrically connected to a common contact and the shallow trenches isolated in the same way as described above.

(22) Processing steps such as wafer thinning or grinding may optionally follow to define the thickness of the wafer 102. The thickness of the wafer influences the on-resistance of the diode due to the dependence of device resistance on bulk semiconductor material thickness and conductivity. Following thinning or grinding, a back metal contact 121 may be formed on the substrate as illustrated in FIG. 2A. The back metal contact 121 is formed on second major surface 122 of the wafer 102 where the second major surface 122 of the wafer opposes the first major surface 110.

(23) The back metal contact 121 is arranged to form an ohmic contact to the semiconductor substrate 104. The semiconductor substrate 104 is in electrical contact with the conductive material 114 of the deep trenches 108a via the diffusion layers 112 formed around the deep trenches 108b. The diffusion layers 112 of the shallow trenches 108b are in electrical contact with the conductive material 114 of the shallow trenches 108b which is in turn in contact with the common contact 116. In this way, the back metal contact 120 and the common contact form external contacts of the semiconductor device 100 in accordance with embodiments.

(24) Following formation of the back metal contact 121 the wafer may optionally be moulded in a package material. The final processing step may be singulation or dicing of the wafer into individual semiconductor devices thus arriving at the semiconductor device 102 in accordance with embodiments of the present disclosure.

(25) Referring now to FIGS. 2A to 2C, the current paths during operation, in this case breakdown mode of operation, of the semiconductor device will now be described. In overview the current path through the device may be characterised as: 1) vertical from the back metal contact 121 to the deep trenches 108a; 2) horizontal from the deep trenches to 108a to the adjacent shallow trenches 108b through the semiconductor layer 106; and 3) vertical from the shallow trenches 108b to the common contact 116.

(26) In more detail, the first vertical current flow from the back metal contact 121 to the deep trenches 108a may be characterised as flowing from the back metal contact 121 through the substrate and diffusion layer 112 of the deep trench 108a into the electrically conductive material 114 of the deep trench. The horizontal current flow may be characterised as: 1) flowing from the electrically conductive material 114 of the deep trench through the pn junction formed by the diffusion layer 112 of the deep trench 108a and the semiconductor layer 106; 2) through the semiconductor layer 106; and 3) through the pn junction formed by semiconductor layer 106 and the diffusion layer 112 of the shallow trench 108b. The second vertical current flow from the shallow trenches 108b to the common contact 116 may be characterised as flowing from the electrically conductive material 114 of the shallow trench 108b to the common contact 116.

(27) In this way the semiconductor device according to embodiments may be broadly characterised as an arrangement of back-to-back diodes as illustrated in FIG. 2B. A first diode 124 in the back to back arrangement is formed by the pn junction formed by the diffusion layer 112 of the deep trench 108a and the semiconductor layer 106. A second diode in the back to back arrangement is formed by the pn junction of the semiconductor layer 106 and the diffusion layer 112 of the shallow trench 108b. The terminals of the back-to-back diode arrangement are formed by the common contact 116 and the back metal contact 120.

(28) In the context of the present application breakdown mode referred to above is the operation of the device where, provided that the voltage across the device is smaller than the breakdown voltage only a small leakage current will flow. Therefore, in order to drive current through the device, the voltage drop across the device has to be larger than the breakdown voltage. During a typical operation of the device such as draining unwanted stress current to ground the device will operate in breakdown mode. One of the two pn-junctions (either deep trench to substrate layer or shallow trench to substrate layer is in breakdown mode (avalanche mode). The other pn-junction is in forward bias mode.

(29) In embodiments, where the semiconductor device comprises multiple alternating deep and shallow trenches as illustrated in FIG. 2A, the semiconductor device according to embodiments may be characterised as a network of back-to-back (that is, cathode to cathode, or anode to anode) first and second diodes 124, 126 as illustrated in FIG. 2C. In the arrangements of FIGS. 2A and 3, pn junctions are formed by each of the diffusion layer 112 of the deep trench 108a and the semiconductor layer 106 and pn junctions are formed by the semiconductor layer 106 and each of the diffusion layer 112 of the shallow trench 108b. In this way the arrangements of FIGS. 2A and 3 can be seen to contain multiple back to back pn junctions, that is, one back to back diode arrangement for each pair of deep and shallow trenches formed in the semiconductor layer 106 such that it is possible to form a network of multiple back to back diodes.

(30) Optionally, the resistance for each current path (every horizontal arrow for horizontal current plus the according current paths in the deep and shallow trenches) is identical. This can be achieved by having similar resistance-per-length for the shallow and deep trenches, and a similar thickness of the conducting material within each trench. If the resistance for each path is identical, than the current distribution between the different paths will be equal. This results in a constant current density of the horizontal current along the trenches therefore and not dependent on the depth of the current within the device. In this way, current crowding can be minimised and the current carrying capability of the total device will be maximised. Current crowding has the effect that locally the critical current density will be reached, whilst the other regions have not yet reached their maximum current capability. If all of regions of the pn-junctions reach the critical current density at the same time for the same applied external voltage current crowding can approach zero.

(31) In embodiments, an isolating layer 310 may be arranged between the semiconductor substrate 104 and the semiconductor layer 106 as illustrated in FIG. 3. The isolating layer 310 may be an oxide such as SiO.sub.2. One embodiment is to start the processing with a SOI wafer (Silicon on insulator). SOI wafers are commercially available with different doping levels for the two silicon layers and with different thicknesses of the silicon layers and the sandwiched oxide layer. For example, bonded silicon on SOI wafers may be used to form the sandwiched oxide layers. The isolating layer 310 serves isolates the semiconductor substrate 104 from the semiconductor layer 106 and eliminates any parasitic diodes and/or transistors formed by the semiconductor substrate 104, the semiconductor layer 106 and the diffusion layer 112 of the deep trenches 108a and shallow trenches 108b. By eliminating any parasitic diodes and/or transistors the distance from the bottom of the shallow trenches 108b to the semiconductor substrate 104 can be reduced without increasing parasitic diodes and/or transistors. Furthermore, because the depth of the shallow trenches is increased the junction area of the pn junction formed by semiconductor layer 106 and the diffusion layer 112 of the shallow trench 108b increases. The larger the area of the junction the larger the current carrying capability of the device.

(32) With reference to FIG. 4, the semiconductor device 400 may be arranged as a single diode instead as a back-to-back diode (or a so-called open base transistor). As with the arrangements of FIGS. 2A and 3, the semiconductor device 400 may be formed on a semiconductor wafer 102 and the semiconductor wafer may comprise a semiconductor substrate 104 and a semiconductor layer 106 may be formed on the semiconductor substrate 104. The semiconductor layer 106 may be formed on the semiconductor substrate 104 by any appropriate process as discussed above with reference to FIGS. 1A to 1D. The semiconductor substrate 104 may be more highly doped than the semiconductor layer 106 and in this regard the semiconductor substrate 104 may be doped in the region 1e18 cm.sup.3 to 1e20 cm.sup.3 and the semiconductor layer 106 may be doped in the region 1e14 cm.sup.3 to 1e17 cm.sup.3. The semiconductor substrate 104 may be degenerately doped when compared to the semiconductor layer 106. In this way, the semiconductor substrate 104 may be considered have low electrical resistance or in other words the semiconductor substrate 104 may be considered to be low ohmic.

(33) The conductivity type of the semiconductor substrate 104 may be the same as the conductivity type of the semiconductor layer 106. For example, the semiconductor layer 106 may n-type and the semiconductor substrate 104 may be n-type. Alternatively, as illustrated in FIG. 4, the conductivity type of the semiconductor substrate 104 may be opposite to the conductivity type of the semiconductor layer 106. For example, the semiconductor layer 106 may p-type and the semiconductor substrate 104 may be n-type.

(34) The method of manufacturing the semiconductor device 400 is broadly the same as that illustrated in and described above with reference to FIGS. 1a to 1F. However, with reference to FIG. 4, the diffusion layer 112 encasing the deep and shallow trenches may be of opposite conductivity types. That is the shallow trench 108b may include a p type diffusion layer 112 and the deep trench 108a may comprise an n type conductivity type as the diffusion layer 112. The conductivity type of the semiconductor substrate 104 may be of the same type as the diffusion layer 112 encasing the deep trench 108a and in the present example of FIG. 4, the conductivity type of the semiconductor substrate 104 may be n type. The conductivity type of the semiconductor layer 106 may be opposite to the conductivity type of the semiconductor substrate 104. In the example of FIG. 4, the conductivity type of the semiconductor layer 106 may be p type and the conductivity type of the semiconductor substrate may be n type.

(35) In the arrangement of FIG. 4, the electrically conductive material 114 formed in the shallow trench 108b is electrically connected to a contact 416 formed on the first major surface 110 of the wafer 102. A back metal contact 120 is formed on second major surface 122 of the wafer 102. The second major surface 122 of the wafer opposes the first major surface 110. The contact 416 may be electrically isolated from the conductive material 114 formed in the deep trench 108a by an appropriate isolating layer 118. The isolating layer 118 may be formed on the first major surface 110 of the wafer 102 prior to formation of the contact 416. Through metal vias 120 or other suitable electrical connections may be made from contact 416 through the isolating layer 118 to the conductive material 114 formed in the shallow trench 108b. As with the arrangement of FIG. 3, an isolating layer which serves to isolate the semiconductor substrate 104 from the semiconductor layer 106 may be included.

(36) In the foregoing, the arrangement of the trenches can be adapted to the required functionality of the semiconductor device. Specifically, the geometry of the trenches can be any appropriate shape such as cylindrical or rectilinear in cross-section, so as to vary the area of the semiconductor junction and thereby vary the current capacity of the device

(37) The arrangement of n type and p type regions as described above may be juxtaposed according to the particular circumstances, and as required by the application of the semiconductor device.

(38) One or more of the arrangements described above may be modified to form a bipolar transistor. A bipolar transistor may be formed by the addition of a further contact to the semiconductor layer 106. The further contact may be formed on the first major surface 110 of the semiconductor wafer 102. The deep trenches may form the emitter and the shallow trenches may form the base of the bipolar transistor. The semiconductor layer having the additional contact thereto may form the base of the bipolar transistor.

(39) In a further alternative of the embodiments, the deep trench may have a diffusion layer of a first conductivity type and the other trench may have two diffusions comprising a deep diffusion having the same conductivity type as the deep trench diffusion layer and the second shallow diffusion having an opposite conductivity type. For example, the deep trench and the deep diffusion may have an n type conductivity. The shallow diffusion may have a p type diffusion. In this way it is possible to form a Shockley diode between the deep and shallow trenches.

(40) In a yet further alternative to the Shockley diode as described above, it is possible to form a silicon controlled rectifier by the addition of a further contact as described with respect to bipolar transistor arrangement described above. The arrangements of the present disclosure may find applications in discrete surge protection devices or the arrangements may be integrated on an integrated circuit to provide on chip surge protection.

(41) In the context of the present disclosure, conductivity type of a semiconductor of a semiconductor crystal, wafer, layer or substrate identifies the majority charge carrier in the semiconductor. The two types of materials are n-type and p-type. The majority current carriers in n-type material are electrons. The majority current carriers in p-type material are holes.

(42) Particular and preferred aspects of the present disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

(43) The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigate against any or all of the problems addressed by the present invention. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived there from. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

(44) Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

(45) Term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.