An electrostatic discharge (ESD) protection device includes a semiconductor layer having a first doped region, a second doped region, and an intrinsic region formed therein, and a plurality of insulating elements respectively formed therein. The plurality of insulating elements is respectively formed in a portion of the semiconductor layer between the first, second and third doped regions. The intrinsic region is formed at least in the semiconductor layer between one of the second and third regions and the other one of the second and third regions or between one of the second and third regions and the first region. The first doped region is formed with a first conductivity type, and the second and third doped regions are formed with a second conductivity type opposite to the first conductivity type.

A light emitting device according to an embodiment includes a substrate; first to Mth light emitting cells (where M is a positive integer of two or more) which are arranged on the substrate so as to be spaced apart from each other; and first to (M−1)th interconnection wires which electrically connect the first to Mth light emitting cells in series, wherein an mth light emitting cell (where 1≦m≦M) includes a first conductive type semiconductor layer, an active layer and a second conductive type semiconductor layer, which are sequentially arranged on the substrate, and wherein an nth interconnection wire (where 1≦n≦M−1) interconnects the first conductive type semiconductor of the nth light emitting cell with the second conductive type semiconductor of the (n+1)th light emitting cell, and has a plurality of first branch wires which are spaced apart from each other.

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

The present invention belongs to the technical field of semiconductors and discloses a copolar integrated diode, including a plurality of diode structures sharing anodes or cathodes. The copolar integrated diode comprises a semiconductor substrate; a low-doped drift region is doped on the semiconductor substrate; two or more electrodes are connected to the low-doped drift region; wherein, between the low-doped drift region and the semiconductor substrate or in the case of forming a PN junction in the low-doped drift region, the distances from the two or more electrodes to the PN junction of the diode structure are different. The present invention provides an integrated structure of a plurality of diodes, which is low in space occupancy and high in security.

A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die.

A diode device of a transient voltage suppressor (TVS) is disclosed. The diode device includes a substrate, a first well, a second well, a first electrode and a second electrode. The substrate has a first surface. The first well is formed in the substrate and near the first surface. The second well is formed in the substrate and near the first surface. There is a gap between the first well and the second well. The first electrode is electrically connected with the first well. The second electrode is electrically connected with the second well. A current path is formed from the first electrode, the first well, the substrate, the second well to the second electrode. The current path passes through a plurality of PN junctions to form an equivalent circuit having a plurality of equivalent capacitances coupled in series.

A semiconductor device includes a semiconductor substrate and a first semiconductor element. The semiconductor substrate has a circuit core area. The first semiconductor element is arranged on the semiconductor substrate and at least partially surrounds the periphery of the circuit core area. A layout area of the first semiconductor element is larger than a layout area of any of the semiconductor elements in the circuit core area.

A semiconductor device includes a semiconductor layer located between first and second electrodes. The contact location of the semiconductor layer with the first electrode forms a first contact plane. The semiconductor layer includes a first-conductivity-type first semiconductor region in contact with the first electrode, a second-conductivity-type second semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode, a second-conductivity-type third semiconductor region located between the first electrode and the second semiconductor region and contacting the first electrode and having a higher impurity concentration than that of the second semiconductor region, and a second-conductivity-type fourth semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode. The fourth semiconductor region is narrower than the second semiconductor region, shallower than the second semiconductor region, and has a lower impurity concentration than that of the third semiconductor region.

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Provided is a semiconductor element in which a two-dimensional hole gas with an enough concentration can exist, even though the p-type GaN layer is not provided on the topmost surface of the polarization super junction region.

The semiconductor element comprises a polarization super junction region comprising an undoped GaN layer 11 with a thickness a [nm] (a is not smaller than 10 nm and not larger than 1000 nm), an Al.sub.xGa.sub.1-xN layer 12 and an undoped GaN layer 13. The Al composition x and the thickness t [nm] of the Al.sub.xGa.sub.1-xN layer 12 satisfy the following equation

t≧α(a)x.sup.β(a)

Where α is expressed as Log (α)=p.sub.0+p.sub.1 log (a)+p.sub.2{log (a)}.sup.2 (p.sub.0=7.3295, p.sub.1=−3.5599, p.sub.2=0.6912) and β is expressed as β=p′.sub.0+p′.sub.1 log (a)+p′.sub.2{log (a)}.sup.2 (p′.sub.0=−3.6509, p′.sub.1=1.9445, p′.sub.2=−0.3793).