The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

A semiconductor device includes a transistor cell region and a transition region. The transistor cell region includes a first portion of a super junction structure and a first contact structure electrically connecting a first load electrode with first source zones of transistor cells. The first source zones are formed on opposite sides of the first contact structure. The transition region directly adjoins to the transistor cell region and includes a second portion of the super junction structure and a second contact structure electrically connecting the first load electrode with a second source zone. The second source zone is formed only at a side of the second contact structure oriented to the transistor cell region.

Device structures and fabrication methods for a device structure. One or more trench isolation regions are formed in a substrate to surround a device region. A base layer is formed on the device region. First and second emitter fingers are formed on the base layer. A portion of the device region extending from the first emitter finger to the second emitter finger is free of dielectric material.

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.

A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.

A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer; etching the first base layer; forming a second base layer on the intrinsic base semiconductor layer adjacent the first base layer; removing the first mask; applying a second mask to the base layers; simultaneously etching the layers to produce extrinsic bases of reduced cross dimensions; disposing spacers on the extrinsic bases; etching around the bases leaving the intrinsic base semiconductor layer under the bases and spacers; implanting ions into sides of the intrinsic base semiconductor layer under the first extrinsic base to form a first emitter/collector junction and into sides of the intrinsic base semiconductor layer under the second extrinsic base to form a second emitter/collector junction; depositing semiconductor material adjacent to the junctions and the trenches; and removing the applied second mask.

Integrated circuits with lateral bipolar transistors and methods for fabricating the same are provided. An exemplary integrated circuit includes a semiconductor layer overlying an insulator layer. The semiconductor layer includes a first region having a first thickness and a trench region having a second thickness less than the first thickness. The integrated circuit further includes an isolation region formed over the trench region of the semiconductor layer. Also, the integrated circuit includes a lateral bipolar transistor including a base formed in the trench region of the semiconductor layer, an emitter, and a collector.

Integrated circuits with lateral bipolar transistors and methods for fabricating the same are provided. An exemplary integrated circuit includes a semiconductor layer overlying an insulator layer. The semiconductor layer includes a first region having a first thickness and a trench region having a second thickness less than the first thickness. The integrated circuit further includes an isolation region formed over the trench region of the semiconductor layer. Also, the integrated circuit includes a lateral bipolar transistor including a base formed in the trench region of the semiconductor layer, an emitter, and a collector.