The present invention discloses a two-terminal vertical 1T-DRAM and a method of fabricating the same. According to one embodiment of the present invention, the two-terminal vertical 1T-DRAM includes a cathode layer formed of a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed of a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

An electrically programmable fuse structure and a semiconductor device are disclosed. The electrically programmable fuse structure comprises a cathode, a fuse link and an anode, the fuse link connecting the cathode to the anode, the cathode connected to the fuse link at a junction, wherein the cathode comprises a plurality of conductive branches arranged to form a converging side and a diverging side, and the converging side of the cathode is connected to the junction so as to be connected to the fuse link.

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

A semiconductor device includes interlayer insulating layers and horizontal structures alternately and repeatedly disposed on a semiconductor substrate, separation structures extending in a direction perpendicular to an upper surface of the semiconductor substrate on the semiconductor substrate, to extend in a first horizontal direction parallel to the upper surface of the semiconductor substrate, and vertical structures disposed between the separation structures. Each of the horizontal structures includes a plurality of semiconductor regions, and the plurality of semiconductor regions of each of the plurality of semiconductor regions include a first semiconductor region and a second semiconductor region sequentially arranged in a direction away from a side surface of a corresponding one of the vertical structures and having different conductivity types.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.