Patent classifications
H01L27/14643
Image sensor with dual trench isolation structure
In some embodiments, the present disclosure relates to an image sensor. The image sensor comprises a substrate. A photodetector is in the substrate and includes a semiconductor guard ring extending into a first side of the substrate. A shallow trench isolation (STI) structure extends into the first side of the substrate. An outer isolation structure extends into a second side of the substrate, opposite the first side of the substrate, to the STI structure. The STI structure and the outer isolation structure laterally surround the photodetector. An inner isolation structure extends into the second side of the substrate and overlies the photodetector. The inner isolation structure is vertically separated from the photodetector by the substrate. Further, the outer isolation structure laterally surrounds the inner isolation structure.
LIGHT RECEIVING ELEMENT AND LIGHT RECEIVING DEVICE
A light receiving element including: a semiconductor substrate; a photoelectric conversion unit (PD) in the semiconductor substrate that converts light into electric charges; a first electric charge accumulation unit (MEM) in the semiconductor substrate to which the electric charges are transferred from the photoelectric conversion unit; a first distribution gate on a front surface of the semiconductor substrate that distributes the electric charges from the photoelectric conversion unit to the first electric charge accumulation unit; a second electric charge accumulation unit (MEM) in the semiconductor substrate to which the electric charges are transferred from the photoelectric conversion unit; and a second distribution gate on the front surface of the semiconductor substrate that distributes the electric charges from the photoelectric conversion unit to the second electric charge accumulation unit, in which the first and second distribution gates each have a pair of buried gate portions.
OPTICAL SENSOR
An optical sensor includes an avalanche multiplication region including a first multiplication region having a first conductive type and a second multiplication region having a second conductive type, each of the first multiplication region and the second multiplication region being formed in a layer shape, a charge collection region having the second conductive type disposed on a first side of the second multiplication region, and a first conductive region having the first conductive type disposed on the first side of the second multiplication region. The second multiplication region has a first portion overlapping the charge collection region in a thickness direction of the first multiplication region and the second multiplication region and a second portion overlapping the first conductive region in the thickness direction. A concentration of impurities in the first portion is higher than a concentration of impurities in the second portion.
IMAGE SENSOR WITH CONTROLLED SPAD AVALANCHE
There is provided an image sensor employing an avalanche diode. The image sensor includes a plurality of pixel circuits arranged in a matrix, a plurality of pulling circuits and a global current source circuit. Each of the plurality of pixel circuits includes a single photon avalanche diode (SPAD) and a floating diffusion. Each of the plurality of pulling circuits is arranged corresponding to one pixel circuit column. The global current source circuit is used to form a current mirror with each of the plurality of pulling circuits. The floating diffusion is used to record a voltage of one photon event detected by the SPAD in an exposure period.
SOLID-STATE IMAGING DEVICE
A solid-state imaging device includes: pixels arranged in a matrix; a vertical signal line provided for each column, conveying a pixel signal; a power line provided for each column, proving a power supply voltage; and a feedback signal line provided for each column, conveying a signal from a peripheral circuit to a pixel, in which each of the pixels includes: an N-type diffusion layer; a photoelectric conversion element above the N-type diffusion layer; and a charge accumulation node between the N-type diffusion layer and the photoelectric conversion element, accumulating signal charge generated in the photoelectric conversion element, the feedback signal line, a metal line which is a part of the charge accumulation node, the vertical signal line, and the power line are disposed in a second interconnect layer, and the vertical signal line and the power line are disposed between the feedback signal line and the metal line.
IMAGING DEVICE
An imaging device including: a first imaging cell including a first photoelectric converter that generates a first signal; and a second imaging cell including: a second photoelectric converter that generates a second signal; and a capacitor having a first and second terminal, the first terminal electrically coupled to second photoelectric converter. An area of the first photoelectric converter is greater than an area of the second photoelectric converter in a plan view, the first imaging cell has a first number of saturation charges, and the second imaging cell has a second number of saturation charges, the first number of saturation charges is greater than the second number of saturation charges, and the capacitor has capacitance that causes the second number of saturation charges of the second imaging cell to become greater than the first number of saturation charges of the first imaging cell.
Handheld Backscatter Scanning Systems With Different Detector Panel Configurations
The present specification provides a detector for an X-ray imaging system. The detector includes at least one high resolution layer having high resolution wavelength-shifting optical fibers, each fiber occupying a distinct region of the detector, at least one low resolution layer with low resolution regions, and a single segmented multi-channel photo-multiplier tube for coupling signals obtained from the high resolution fibers and the low resolution regions.
IMAGING APPARATUS
An imaging apparatus includes a pixel region including a first substrate section and pixels, and a peripheral region including a second substrate section and no pixels. Each of the pixels includes a first electrode; a second electrode; a photoelectric conversion layer that is disposed between the first electrode and the second electrode; and a charge accumulation region disposed in the first substrate section. The pixel region includes first penetrating electrodes that electrically connect the first electrode to the charge accumulation region. The peripheral region includes second penetrating electrodes. An areal density of the first penetrating electrodes that is a ratio of an area of the first penetrating electrodes to an area of the pixel region is different from an areal density of the second penetrating electrodes that is a ratio of an area of the second penetrating electrodes to an area of the peripheral region.
TRANSISTOR STRUCTURES
Transistor structures for a transistor may include a first source-drain region, a second source-drain region, and a channel region between the first and second source-drain regions overlapped by a gate structure. Transistor structures may be formed in a well of a first doping type. Isolation structures having the first doping type may be formed within the well. A lightly doped implant region of a second doping type for each of the source-drain regions may be formed within the well and separated from the isolation structures. A heavily doped surface implant region of the first doping type may extend across the surface of the well and cover the lightly doped implant region of each source-drain region. The surface implant region may be formed by patterning or by a blanket implantation process across the transistor structures.
INTEGRATED SENSOR
Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in a plurality of time-binning pixels. In some embodiments, an optical component for optical rejection is provided in between a waveguide and the time-binning pixel and configured to block at least some excitation photons in a pulsed light stream from arriving at the photodetection region. In some embodiments, the time-binning pixel does not comprise a time-gated transistor for electronic rejection configured to block a transfer of charge carriers associated with excitation photons in the pulsed light stream.