Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response to incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

Example embodiments relate to image sensors for time delay and integration imaging and methods for imaging using an array of photo-sensitive elements. One example image sensor for time delay and integration imaging includes an array of photo-sensitive elements that includes a plurality of photo-sensitive elements arranged in rows and columns of the array. Each photo-sensitive element includes an active layer configured to generate charges in response to incident light on the active layer. Each photo-sensitive element also includes a charge transport layer. Further, each photo-sensitive element includes at least a first and a second gate, each separated by a dielectric material from the charge transport layer. The array of photo-sensitive elements is configured such that the second gate of a first photo-sensitive element and the first gate of a second photo-sensitive element in a direction along a column of the array are configured to control transfer of charges.

Disclosed are infrared (IR) light detectors. The detectors operate by generating hot electrons in a metallic absorber layer on photon absorption, the electrons being transported through an energy barrier of an insulating layer to a metal or semiconductor conductive layer. The energy barrier is set to bar response to wavelengths longer than a maximum wavelength. Particular embodiments also have a pattern of metallic shapes above the metallic absorber layer that act to increase photon absorption while reflecting photons of short wavelengths; these particular embodiments have a band-pass response.

A pixel circuit includes a photodiode in semiconductor material to accumulate image charge in response to incident light. A tri-gate charge transfer block coupled includes a single shared channel region the semiconductor material. A transfer gate, shutter gate, and switch gate are disposed proximate to the single shared channel region. The transfer gate transfers image charge accumulated in the photodiode to the single shared channel region in response to a transfer signal. The shutter gate transfers the image charge in the single shared channel region to a floating diffusion in the semiconductor material in response to a shutter signal. The switch gate is configured to couple the single shared channel region to a charge storage structure in the semiconductor material in response to a switch signal.

A pixel circuit includes a photodiode in semiconductor material to accumulate image charge in response to incident light. A tri-gate charge transfer block coupled includes a single shared channel region the semiconductor material. A transfer gate, shutter gate, and switch gate are disposed proximate to the single shared channel region. The transfer gate transfers image charge accumulated in the photodiode to the single shared channel region in response to a transfer signal. The shutter gate transfers the image charge in the single shared channel region to a floating diffusion in the semiconductor material in response to a shutter signal. The switch gate is configured to couple the single shared channel region to a charge storage structure in the semiconductor material in response to a switch signal.

The disclosure relates to a demodulator including a pinned photodiode, at least one storage node, at least one transfer gate connected between the storage node and the pinned photodiode. The pinned photodiode includes a p-doped epitaxial semiconductor layer, a n-doped semiconductor region formed within the epitaxial semiconductor layer and creating therewith a lower junction and at least one lateral junction substantially perpendicular to the lower junction, a p+ pinning layer formed on top of said semiconductor region. The demodulator further includes a generating unit configured to generate minority and majority carriers at said lateral junction and to form a lateral photodiode.

An image sensor may include: a pixel array including a plurality of pixels; and a timing controller configured to control the pixel array according to an operation mode of the pixel array. The operation mode may be any one of a first mode in which the plurality of pixels operate according to a global shutter method and a second mode in which the plurality of pixels operate according to a dual conversion gain method.

An imaging device 100 includes a pixel array PA. A first period, a third period, and a second period appear in this order in one frame. During the first period, pixel signal readout is performed on at least one first row in the pixel array PA. During the second period, pixel signal readout is performed on at least one second row in the pixel array PA. At least one of the at least one first row or the at least one second row includes two rows in the pixel array PA. During the third period, no pixel signal readout is performed on the rows in the pixel array PA. Each of the first period and the second period is one of the high-sensitivity exposure period and the low-sensitivity exposure period. The third period is the other of the high-sensitivity exposure period and the low-sensitivity exposure period.

A charge-coupled device includes an array of insulated electrodes vertically penetrating into a semiconductor substrate. The array includes rows of alternated longitudinal and transverse electrodes. Each end of a longitudinal electrode of a row is opposite and separated from a portion of an adjacent transverse electrode of that row. Electric insulation walls extend parallel to one another and to the longitudinal electrodes. The insulation walls penetrate vertically into the substrate deeper than the longitudinal electrodes. At least two adjacent rows of electrodes are arranged between each two successive insulation walls.

An imaging device includes a plurality of photodiodes arranged in a photodiode array to generate charge in response to incident light. The plurality of photodiodes includes first and second photodiodes. A shared floating diffusion receives charge transferred from the first and second photodiodes. An analog to digital converter (ADC) performs a first ADC conversion to generate a reference readout in response to charge in the shared floating diffusion after a reset operation. The ADC is next performs a second ADC conversion to generate a first half of a phase detection autofocus (PDAF) readout in response to charge transferred from the first photodiode to the shared floating diffusion. The ADC then performs a third ADC conversion to generate a full image readout in response to charge transferred from the second photodiode combined with the charge transferred previously from the first photodiode in the shared floating diffusion.