Structures and related techniques for control of two-dimensional electron gas (2DEG) charge density in gallium nitride (GaN) devices are disclosed. In one aspect, a GaN device includes a compound semiconductor substrate, a source region formed in the compound semiconductor substrate, a drain region formed in the compound semiconductor substrate and separated from the source region, a 2DEG layer formed in the compound semiconductor substrate and extending between the source region and the drain region, a gate region formed on the compound semiconductor substrate and positioned between the source region and the drain region, and a plurality of isolated charge control structures disposed between the gate region and the drain region.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.

An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

A Schottky barrier diode according to the present disclosure includes an n-type semiconductor substrate, one or more p-type guard rings provided on a side of an upper surface of the semiconductor substrate, an anode electrode provided on the upper surface of the semiconductor substrate, a cathode electrode provided on a rear surface of the semiconductor substrate and an insulating film provided on an inner guard ring on an innermost side among the one or more guard rings, wherein the anode electrode rides on the insulating film and has its end portion provided just above the inner guard ring, the anode electrode and the inner guard ring are provided away from each other, and a thickness of the insulating film is 1.0 μm or more.

A nitride-based semiconductor device includes first and second nitride-based semiconductor layers, first electrodes, doped nitride-based semiconductor layers, a second electrode, and gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion surrounding the active portion. The first electrodes are disposed over the second nitride-based semiconductor layer. The first electrodes, doped nitride-based semiconductor layers, the gate electrode, and the second electrode are disposed over the second nitride-based semiconductor layer. Each of the doped nitride-based semiconductor layers has a side surface facing away from the second electrode and spaced apart from the interface.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a pair of first electrodes, a second electrode, a doped nitride-based semiconductor layer, and a pair of gate electrodes. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer. The first and second nitride-based semiconductor layers collectively have an active portion and an electrically isolating portion that is non-semi-conducting and surrounds the active portion to form an interface therebetween. The first electrodes are disposed over the second nitride-based semiconductor layer. The second electrode are disposed over the second nitride-based semiconductor layer and between the first electrodes. The doped nitride-based semiconductor layer is disposed over the second nitride-based semiconductor layer and between the first electrodes and surrounding the second electrode. The gate electrodes are disposed over the doped nitride-based semiconductor layer and located at opposite sides of the second electrode.

A semiconductor device includes a drain electrode, a first source electrode, a second source electrode, a first gate electrode, and a second gate electrode. The first gate electrode is arranged between the first source electrode and the drain electrode. The first gate electrode extends along a first direction. The second gate electrode is arranged between the second source electrode and the drain electrode. The second gate electrode extends along the first direction. The first gate electrode is arranged above a first imaginary line substantially perpendicular to the first direction in a top view of the semiconductor device and the second gate electrode is arranged below a second imaginary line substantially perpendicular to the first direction in the top view of the semiconductor device.

Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.