The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

A semiconductor device includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed on the buffer layer, a barrier layer disposed on the buffer layer, and a passivation layer disposed on the barrier layer. The semiconductor device further includes a device isolation region that extends through the passivation layer, the barrier layer, and at least a portion of the channel layer, and encloses a first device region of the semiconductor device. A damage concentration of the device isolation region varies along a depth direction, and is highest near a junction between the barrier layer and the channel layer.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a fin including silicon. A gate structure is over the fin, the gate structure having a center. A conductive source trench contact is over the fin, the conductive source trench contact having a center spaced apart from the center of the gate structure by a first distance. A conductive drain trench contact is over the fin, the conductive drain trench contact having a center spaced apart from the center of the gate structure by a second distance, the second distance greater than the first distance by a factor of three.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture. At least two of the current apertures have different dimensions such that interfaces formed between the high resistivity regions and the current apertures misalign with each other. The gate electrode aligns with the current aperture.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of the substrate base, the semiconductor layer comprising a second dopant type and having an upper surface; and a semiconductor plug assembly comprising a semiconductor plug disposed within the semiconductor layer, the semiconductor plug extending from an upper surface of the semiconductor layer and having a depth at least equal to a thickness of the semiconductor layer, the semiconductor plug having a first boundary, the first boundary formed within the semiconductor layer, and having a second boundary, the second boundary formed within the semiconductor layer and disposed opposite the first boundary, wherein the first boundary and second boundary extend perpendicularly to the surface of the substrate base.

An integrated circuit includes a device including an active region of the device, where the active region of the device includes a channel region having a transverse and a lateral direction. The device further includes an isolation region adjacent to the active region in a traverse direction from the active region, where the isolation region includes a first region located in a transverse direction to the channel region. The isolation region further includes a second region located in a lateral direction from the first region. The first region of the isolation region is under a stress of a first type and the second region of the isolative region is one of under a lesser stress of the first type or of under a stress of a second type being opposite of the first type.

A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate insulating film, a gate electrode, first contacts, and second contacts. The gate insulating film is on the semiconductor layer between the plurality of diffusion layers. The gate electrode is on the gate insulating film. The first contacts include silicide layers of the same material which are on the gate electrode and the diffusion layers respectively, and first metal layers on the silicide layers. The second contacts are on the first contacts.