A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.

A method of forming a power semiconductor device is provided. The method includes the step of providing a semiconductor substrate. The semiconductor substrate has an active region and a termination region surrounding the active region. An epitaxial layer is disposed on the semiconductor substrate. The etching process is conducted to the epitaxial layer to form a first trench and a second trench. The first trench is disposed at the active region and the second trench is disposed at the termination region. A second trench width of the second trench is less than a first trench width of the first trench. An oxidation process is conducted to form a dielectric structure. The dielectric structure has a first dielectric layer disposed on the first trench and a dielectric area fully covers a trench area of the second trench.

A silicon carbide semiconductor device includes a drift layer of a first conductivity type, a source region of the first conductivity type, an active trench formed in penetration through the source region, a base region, a termination trench formed around the active trench, a gate insulating film formed on a bottom surface, a side surface of the active trench, a gate electrode embedded and formed in the active trench with the gate insulating film interposed therebetween, a protective diffusion layer of a second conductivity type formed in a lower portion of the active trench and a part of a lower portion of the termination trench and having a first impurity concentration, and a termination diffusion layer of the second conductivity type formed on an outside of the protective diffusion layer in the lower portion of the termination trench and having a second impurity concentration lower than the first impurity concentration.

A semiconductor device includes a semiconductor layer including a Ga.sub.2O.sub.3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga.sub.2O.sub.3-based single crystal.

A SiC semiconductor device includes SiC chip having main surface that includes first surface, second surface hollowed in thickness direction at first depth outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a transistor structure formed at an inward portion of the first surface, the transistor structure including a trench gate structure that has a second depth less than the first depth and a trench source structure that has a third depth exceeding the second depth and that adjoins the trench gate structure in one direction, and a dummy structure formed at a peripheral edge portion of the first surface, the dummy structure including a plurality of dummy trench source structures which have the third depth and adjoin each other in the one direction.

A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

A trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.