SEMICONDUCTOR DEVICE

Abstract

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.

Claims

1-24. (canceled)

25. A wide band gap semiconductor device comprising: a semiconductor substrate; a first gate insulating film on the semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on the semiconductor substrate; and a second gate electrode on the second gate insulating film; and a source electrode formed over the semiconductor substrate, the first gate electrode and the second gate electrode, wherein a portion of a surface of the semiconductor substrate between a center of the first gate electrode and a center of the second gate electrode is recessed compared to a portion of a surface of the semiconductor substrate under the center of the first gate electrode and the center of the second gate electrode, wherein the semiconductor substrate comprises an outer peripheral recessed portion that includes a recess, and a part of the source electrode is arranged between the first and second gate electrodes and the recess of the outer peripheral recessed portion and does not intrude into the recess of the outer peripheral recessed portion in a cross section.

26. The wide band gap semiconductor device according to claim 25, wherein a gate pad is formed in a vicinity of one side of the semiconductor substrate.

27. The wide band gap semiconductor device according to claim 26, wherein the gate pad is placed in the middle of the one side of the semiconductor substrate.

28. The wide band gap semiconductor device according to claim 25, wherein a source contact region is formed in a region between the first gate electrode and the second gate electrode.

29. The wide band gap semiconductor device according to claim 28, wherein at least one of the first gate electrode and the second gate electrode is a planer type gate electrode.

30. The wide band gap semiconductor device according to claim 29, wherein a gate finger is formed between the source electrode and the outer peripheral recessed portion of the semiconductor substrate in a cross section.

31. The wide band gap semiconductor device according to claim 30, wherein a height of the gate finger is approximately the same as a height of the source electrode.

32. The wide band gap semiconductor device according to claim 31, wherein the source electrode is made of a material including an aluminum.

33. The wide band gap semiconductor device according to claim 32, wherein the gate finger is made of a material including an aluminum.

34. The wide band gap semiconductor device according to claim 33, wherein a peripheral source electrode is formed between the gate finger and the outer peripheral recessed portion of the semiconductor substrate.

35. The wide band gap semiconductor device according to claim 34, wherein the semiconductor substrate is made of SiC, GaN, or diamond.

36. The wide band gap semiconductor device according to claim 35, further comprising a titanium material between the source electrode and the semiconductor substrate at the source contact region.

37. The wide band gap semiconductor device according to claim 36, wherein the gate insulating film is made of a material including silicon.

38. The wide band gap semiconductor device according to claim 37, wherein the gate electrode is made of a material including a polysilicon.

39. The wide band gap semiconductor device according to claim 38, wherein a surface of the source electrode is dented according to the surface of the semiconductor substrate.

40. The wide band gap semiconductor device according to claim 38, wherein a depth of the recess of the portion of the surface of the semiconductor substrate between the center of the first gate electrode and the center of the second gate electrode is approximately the same as a depth of the recess of the outer peripheral recessed portion.

41. The wide band gap semiconductor device according to claim 38, wherein the recess of the portion of surface of the semiconductor substrate between the center of the first gate electrode and the center of the second gate electrode is fabricated at a same time with the recess of the outer peripheral recessed portion.

42. The wide band gap semiconductor device according to claim 38, wherein an impurity region of P-type material is formed at a surface of the outer peripheral recessed portion.

43. The wide band gap semiconductor device according to claim 27, wherein an aluminum wire is connected to the source electrode.

44. The wide band gap semiconductor device according to claim 43, wherein a surface of the source electrode has an unevenness.

45. The wide band gap semiconductor device according to claim 44, the unevenness is formed according to a shape of a covered object covered by the source electrode.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0049] FIG. 1 is a schematic plan view of a semiconductor device according to a first preferred embodiment of the present invention.

[0050] FIG. 2 is an enlarged view showing a main part of FIG. 1, in which a part is shown perspectively.

[0051] FIG. 3 shows a sectional structure of the semiconductor device in a section taken along of FIG. 2.

[0052] FIG. 4 shows a sectional structure of the semiconductor device in a section taken along IV-IV of FIG. 2.

[0053] FIG. 5 shows a sectional structure of the semiconductor device in a section taken along V-V of FIG. 2.

[0054] FIG. 6 shows a sectional structure of the semiconductor device in a section taken along VI-VI of FIG. 2.

[0055] FIG. 7 is a view showing a cell portion in FIG. 3 in an enlarged manner.

[0056] FIG. 8 is a view showing a first modification of the cell portion.

[0057] FIG. 9 is a view showing a second modification of the cell portion.

[0058] FIG. 10 is a view showing a third modification of the cell portion.

[0059] FIG. 11 is a view showing a fourth modification of the cell portion.

[0060] FIG. 12 is a view showing a fifth modification of the cell portion.

[0061] FIG. 13 is a schematic sectional view of a semiconductor device according to a second preferred embodiment of the present invention.

[0062] FIG. 14 is a schematic sectional view of the semiconductor device according to the second preferred embodiment of the present invention.

[0063] FIG. 15 is a schematic sectional view of a semiconductor device according to a third preferred embodiment of the present invention.

[0064] FIG. 16 is a schematic sectional view of the semiconductor device according to the third preferred embodiment of the present invention.

[0065] FIG. 17 is a schematic sectional view of a semiconductor device according to a first reference embodiment.

[0066] FIG. 18 is a schematic sectional view of the semiconductor device according to the first reference embodiment.

[0067] FIG. 19 is a schematic sectional view of a semiconductor device according to a second reference embodiment.

[0068] FIG. 20 is a schematic sectional view of the semiconductor device according to the second reference embodiment.

[0069] FIG. 21 is a schematic sectional view of a semiconductor device according to a fourth preferred embodiment of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

First Preferred Embodiment

[0070] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0071] FIG. 1 is a schematic plan view of a semiconductor device according to a first preferred embodiment of the present invention.

[0072] The semiconductor device 1 includes a SiC-based MISFET (Metal Insulator Semiconductor Field Effect Transistor). As shown in FIG. 1, the semiconductor device 1 has, for example, a square chip-shaped contour in a plan view. The chip-shaped semiconductor device 1 is sized to have a vertical and horizontal length of about several millimeters in the illustration of FIG. 1. A cell portion 2 and an outer peripheral portion 3 disposed around the cell portion 2 are set on the semiconductor device 1. The outer peripheral portion 3 is, in the present preferred embodiment, formed in an annular shape in a manner surrounding the cell portion 2, but the outer peripheral portion 3 need not particularly be an annular shape as long as it is a region at an outer side of the chip with respect to the cell portion 2.

[0073] The semiconductor device 1 includes a source pad 4, a gate pad 5, and a gate finger 6.

[0074] The source pad 4 is disposed in a region over the cell portion 2. In the present preferred embodiment, the source pad 4 is formed in, for example, a square shape in a plan view in a manner covering substantially the whole of the cell portion 2. In a peripheral edge portion of the source pad 4, a removal region 7 (cross-hatched part in FIG. 1) that surrounds a central region of the source pad 4 is formed along the outer peripheral portion 3. The removal region 7 is selectively recessed at a part thereof toward the central region of the source pad 4. The recess is disposed in its entirety in a region over the cell portion 2, and has the gate pad 5 installed therein.

[0075] The gate finger 6 extends, in a position closer to the outer peripheral portion 3 with respect to a boundary between the cell portion 2 and the outer peripheral portion 3, from the gate pad 5 across the entire removal region 7 along the outer peripheral portion 3. In the present preferred embodiment, a pair of gate fingers 6 are formed in a shape symmetrical with respect to the gate pad 5. Moreover, in the present preferred embodiment, the boundary (the same as the boundary L in FIG. 2) between the cell portion 2 and the outer peripheral portion 3 described above is set, for example, along an inner part with respect to the gate fingers 6 of the removal region 7.

[0076] The cell portion 2 is further formed with a gate trench 8. The gate trench 8 is, in the present preferred embodiment, selectively formed in a region under the source pad 4 in a manner avoiding a region under the gate pad 5. In this region, the gate trench 8 is formed in a manner defining a plurality of unit cells 9. The gate trench 8 may be patterned in, as shown in FIG. 1, a grid shape or in a striped shape. A large number of unit cells 9 are thereby regularly arrayed in a matrix shape (in an array) or a striped shape (linearly) in the cell portion 2. Although, this is not shown, the unit cells 9 may be patterned in another shape such as a honeycomb shape.

[0077] Next, an internal structure of the cell portion 2 and the outer peripheral portion 3 of the semiconductor device 1 will be described.

[0078] FIG. 2 is an enlarged view showing a main part of FIG. 1, in which a part is shown perspectively. Specifically, a structure in a region under the source pad 4 and the gate fingers 6 is shown by solid lines, and the source pad 4 and the gate fingers 6 are shown by broken lines. FIG. 3 shows a sectional structure of the semiconductor device in a section taken along III-III of FIG. 2. FIG. 4 shows a sectional structure of the semiconductor device in a section taken along IV-IV of FIG. 2. FIG. 5 shows a sectional structure of the semiconductor device in a section taken along V-V of FIG. 2. FIG. 6 shows a sectional structure of the semiconductor device in a section taken along VI-VI of FIG. 2.

[0079] The semiconductor device 1 includes a substrate (not shown) made of n.sup.+-type SiC (for example, having a concentration of 1×10.sup.18 to 1×10.sup.21cm.sup.−3) and an n.sup.−-type epitaxial layer 10 made of n.sup.−-type SiC (for example, having a concentration of 1×10.sup.15 to 1×10.sup.17cm.sup.−3) formed on the substrate. The n.sup.−-type epitaxial layer 10 is a layer formed by causing SiC to epitaxially grow on a surface of the substrate. In the present preferred embodiment, the substrate and the n.sup.−-type epitaxial layer 10 are shown as an example of a semiconductor layer of the present invention. Also, the substrate has a thickness of, for example, about 250 μm to 350 μm, and the n.sup.−-type epitaxial layer 10 has a thickness of about 3 μm to 20 μm.

[0080] The n.sup.−-type epitaxial layer 10 has a semiconductor surface 11 with a difference in height formed by being selectively dug down ata part thereof. The difference in height of the semiconductor surface 11 is, in the present preferred embodiment, formed by the gate trench 8 and source trenches 33 (described later) selectively formed in the cell portion 2 and the outer peripheral portion 3 and a low step portion 12 selectively formed in the outer peripheral portion 3. In the following, the semiconductor surface 11 where the gate trench 8, the source trenches 33, and the low step portion 12 are not formed and which is maintained at a height position after epitaxial growth is provided as a base surface 11B, and like a bottom face of the gate trench 8, a bottom face of the source trench 33, and a bottom face of the low step portion 12, the semiconductor surface 11 formed at a relatively low height position with respect to the base surface 11B is provided as a lower surface 11L.

[0081] The gate trench 8, in the present preferred embodiment, includes an inner trench 13 that is used as the gate of a MISFET, an outer trench 14 disposed on an outer side with respect to the inner trench 13, and a contact trench 15 that is pulled out from the outer trench toward the outer peripheral portion 3 to serve as a contact with a gate electrode 16 (described later). The trenches 13 to 15 are integrally formed in a manner communicating with each other.

[0082] As shown in FIG. 2, the inner trench 13 is formed in a grid shape by a plurality of line-shaped trenches crossing each other in a manner defining a plurality of unit cells 9. Terminal portions of the respective lines of the inner trench 13 are connected to each other by the outer trench 14. In other words, the outer trench 14 is formed in a manner surrounding the inner trench 13, and extends across between the terminal portions of mutually adjacent lines of the inner trench 13.

[0083] The contact trenches 15 are formed in line shapes constituted of extension portions of the respective lines of the inner trench 13, and disposed in plural numbers, spaced apart from each other, along the boundary L between the cell portion 2 and the outer peripheral portion 3. In addition, the contact trenches 15 need not be provided for every line of the inner trench 13, and may be provided, for example, for every other line of the inner trench 13. The line-shaped contact trenches 15 are formed in a manner running across the gate fingers 6 in a region under the gate fingers 6. In the present preferred embodiment, the contact trenches 15 have their terminal portions disposed further outside than the gate fingers 6. In other words, the terminal portions of the contact trenches 15 are sticking out further outside than the gate fingers 6.

[0084] Moreover, in the gate trench 8, a gate electrode 16 made of, for example, polysilicon is buried, and a gate insulating film 17 is interposed between the gate electrode 16 and the n.sup.−-type epitaxial layer 10.

[0085] The gate electrode 16 is, for example, as shown in FIG. 3 and FIG. 4, buried up to the base surface 11B in the inner trench 13 and the outer trench 14 formed at positions separated from a region under the gate fingers 6. The gate electrode 16 is thereby also formed in a grid shape, and an upper face of the respective unit cells 9 is exposed without being covered with the gate electrode 16. On the other hand, in the contact trenches 15 formed in a region under the gate fingers 6, the gate electrode 16 has an overlapping portion 18 formed from an opening end of the contact trench 15 in a manner selectively covering the base surface 11B. The overlapping portion 18 is, in the present preferred embodiment, as shown in FIG. 2, formed along the gate fingers 6 in a manner running across the line-shaped contact trenches 15. As shown in FIG. 5 and FIG. 6, also between the overlapping portion 18 and the n.sup.−-type epitaxial layer 10, a gate insulating film 17 is interposed.

[0086] In the cell portion 2, the gate electrode 16 controls formation of an inversion layer (channel) in the unit cell 9. That is, the semiconductor device 1 has a so-called trench-gate type structured MISFET.

[0087] The low step portion 12 is, in the present preferred embodiment, formed across the entire circumference of the outer peripheral portion 3, and thereby surrounds the cell portion 2. The low step portion 12 is formed with a depth equal to or deeper than a depth of the gate trench 8. Thus, in the outer peripheral portion 3, the bottom face (lower surface 11L) of the low step portion 12 is formed at a depth position equal to or deeper than that of the bottom face (lower surface 11L) of the gate trench 8. That depth is, for example, 0.7 μm to 5 μm with reference to the base surface 11B, relative to the depth of the gate trench 8 of 0.7 μm to 3 μm.

[0088] Moreover, in the semiconductor surface 11 having such a difference in height, n-type and p-type impurity regions are selectively formed.

[0089] Specifically, in a surface portion of the n.sup.−-type epitaxial layer 10, a p-type well 19 (for example, having a concentration of 1×10.sup.16 to 1×10.sup.19cm.sup.−3) is formed in a manner extending across the cell portion 2 and the outer peripheral portion 3. On the other hand, a region of a portion under the p-type well 19 in the n.sup.−-type epitaxial layer 10 is an n.sup.−-type drain region 20. In the present preferred embodiment, as shown in FIG. 3, the p-type well 19 is continuously formed, from the cell portion 2 to the low step portion 12 of the outer peripheral portion 3 via a region under the gate fingers 6, in such a manner that its bottomportion follows the base surface 11B. The p-type well 19 is thereby exposed at a side portion of the low step portion 12.

[0090] In the p-type well 19, as shown in FIG. 3, FIG. 5, and FIG. 6, an n.sup.+-type region 21 is formed in a region under the gate fingers 6, and exposed on the base surface 11B of the n.sup.−-type epitaxial layer 10. The n.sup.+-type region 21 is a high concentration region (for example, having a concentration of 1×10.sup.18 to 1×10.sup.21cm.sup.−3) containing an n-type impurity at a higher concentration than that of the n.sup.−-type epitaxial layer 10. In the present preferred embodiment, as shown in FIG. 3, the n.sup.+-type region 21 is continuously formed, from the cell portion 2 to the low step portion 12 of the outer peripheral portion 3 via a region under the gate fingers 6, in such a manner that its bottom portion follows the base surface 11B. The n.sup.+-type region 21 is thereby exposed at a side portion of the low step portion 12.

[0091] In the n.sup.−-type epitaxial layer 10, as shown in FIG. 4 to FIG. 6, a p-type layer 22 (for example, having a concentration of 1×10.sup.16 to 1×10.sup.19cm.sup.−3) is formed in a region under the gate fingers 6 in a manner continuing from the p-type well 19. The p-type layer 22 is, in the present preferred embodiment, formed in a manner extending across a bottom portion and side portion (including a side portion of the terminal portion) of the contact trench 15, and its inner region is in contact with the contact trench 15 (exposed into the contact trench 15). Also, the p-type layer 22 is, at the bottom portion of the contact trench 15, formed to be thicker than a part at a side portion of the contact trench 15.

[0092] Also, in the n.sup.−-type epitaxial layer 10, as shown in FIG. 3 and FIG. 4, a p-type layer 23 (for example, having a concentration of 1×10.sup.16 to 1×10.sup.19cm.sup.−3) serving as an example of a voltage resistant structure of the present invention is formed in the low step portion 12 in a manner continuing from the p-type well 19. The p-type layer 23 is, in the present preferred embodiment, formed in a manner extending across a bottom portion and side portion of the low step portion 12, and its inner region is in contact with the low step portion 12 (exposed into the low step portion 12). In a surface portion of the p-type layer 23, a p.sup.+-type well contact region 24 (for example, having a concentration of 1×10.sup.18 to 1×10.sup.21cm.sup.−3) is formed. In the present preferred embodiment, the p.sup.+-type well contact region 24 is formed in the lower surface 11L of the low step portion 12, and formed in an annular shape in a manner surrounding the cell portion 2.

[0093] Also, outside of the p-type layer 23 in the low step portion 12, a p-type guard ring 25 (for example, having a concentration of 1×10.sup.16 to 1×10.sup.19cm.sup.−3) serving as an example of a voltage resistant structure of the present invention is formed. In the present preferred embodiment, the p-type guard rings 25 are formed in plural numbers, spaced apart from each other, in a manner surrounding the cell portion 2 in the lower surface 11L of the low step portion 12.

[0094] On a surface of the n.sup.−-type epitaxial layer 10, a surface insulating film 26 is formed in a manner extending across the cell portion 2 and the outer peripheral portion 3. The surface insulating film 26 is made of an insulator such as silicon oxide (SiO.sub.2), for example. The surface insulating film 26 is, in the present preferred embodiment, formed such that an inner part 27 on the cell portion 2 becomes thinner than an outer part 28 on the outer peripheral portion 3. In the present preferred embodiment, the inner part 27 has a thickness of 5000 Å or less, and the outer part 28 has a thickness of about 5500 Å to 20000 Å. The surface insulating film 26 may be called an interlayer insulating film when a multilayer wiring structure is disposed thereon, which is not shown in FIG. 2.

[0095] In the surface insulating film 26, contact holes 29 to 31 that selectively expose the respective unit cells 9, the gate electrode 16 (overlapping portion 18), and the p.sup.+-type well contact region 24, respectively, are formed over the entire surface of the n.sup.−-type epitaxial layer 10.

[0096] On the surface insulating film 26, the source pad 4 and the gate fingers 6 are formed.

[0097] The source pad 4 is connected collectively to p.sup.+-type channel contact regions 34 (described later) and n.sup.+-type source regions 32 (described later) of all unit cells 9 and the p.sup.+-type well contact region 24 via the respective contact holes 29 and 31. In other words, the source pad 4 serves as a common electrode to all unit cells 9. Also, as the material for the source pad 4, a metal containing copper (Cu) can be used, and more preferably, a metal containing an Al—Cu-based alloy is used. Because the sheet resistance of the source pad 4 can thereby be reduced, the current density can be increased. Also, the source pad 4 has a thickness (distance from the base surface 11B of the n.sup.−-type epitaxial layer 10 to a surface of the source pad 4) of, for example, 4 μm to 5 μm. In addition, the source pad 4 may have a contact metal made of, for example, a laminated structure (Ti/TiN) of titanium (Ti) and titanium nitride (TiN) at a connection part with the n.sup.−-type epitaxial layer 10.

[0098] The gate fingers 6 are connected to the gate electrode 16 (overlapping portion 18) via the contact hole 30. Also, as the material for the gate fingers 6 and the gate pad 5, similar to that for the source pad 4, a metal containing copper (Cu) can be used, and more preferably, a metal containing an Al—Cu-based alloy is used. Using the same material as that for the source pad 4 allows simultaneously forming the source pad 4, the gate pad 5, and the gate fingers 6.

[0099] Next, the structure of the cell portion 2 will be described in greater detail. FIG. 7 is a view showing the cell portion 2 in FIG. 3 in an enlarged manner.

[0100] In the cell portion 2, as described above, the plurality of unit cells 9 each of which performs a transistor operation are defined in a grid shape by the gate trench 8 (inner trench 13 and outer trench 14). Each unit cell 9 includes an annular n.sup.+-type source region 32, an annular source trench 33 (second trench) surrounded by the n.sup.+-type source region 32, and a p.sup.+-type channel contact region 34 formed in an island shape inside the source trench 33. The p.sup.+-type channel contact region 34 is surrounded by the source trench 33 at its periphery. Also, each unit cell 9 is sized to have a vertical and horizontal length of, for example, about 3 μm to 10 μm in the illustration of FIG. 7.

[0101] Specifically, an n.sup.+-type source region 32 is formed in a surface portion of the p-type well 19 in the cell portion 2, and exposed on the base surface 11B of the n.sup.−-type epitaxial layer 10. In addition, a part within the cell portion 2 of the p-type well 19 is a p-type channel region 35 which is disposed in a manner contacting the n.sup.+-type source region 32 and in which a channel is formed at the time of a transistor operation.

[0102] Moreover, the gate trench 8 and the source trench 33 are formed in a manner penetrating through the n.sup.+-type source region 32 and the p-type channel region 35 (p-type well 19) to reach the n.sup.−-type drain region 20. The gate trench 8 and the source trench 33 are, in the present preferred embodiment, formed with the same width and the same depth, but may be different in depth from each other. For example, the source trench 33 may be shallower or may be deeper than the gate trench 8.

[0103] Each unit cell 9 is separated into a prismatic portion 36 surrounded by the source trench 33 and an annular portion 37 disposed between the source trench 33 and the gate trench 8 and spaced apart from the prismatic portion 36 by the source trench 33. In the present preferred embodiment, the width W.sub.1 of the annular portion 37 (distance between the source trench 33 and the gate trench 8) is, for example, 0.5 μm to 2.0 μm.

[0104] In a top portion of the prismatic portion 36, a p.sup.+-type channel contact region 34 (for example, having a concentration of 1×10.sup.18 to 1×10.sup.21cm.sup.−3) is formed in a manner exposed on the base surface 11B of the n.sup.−-type epitaxial layer 10. Accordingly, the p.sup.+-type channel contact region 34 forms a part of the side face of the source trench 33. The p.sup.+-type channel contact region 34, in the present preferred embodiment, has its deepest portion at a position higher than that of a bottom portion of the source trench 33, but the deepest portion is not particularly necessary at this position. As long as an uppermost portion of the p.sup.+-type channel contact region 34 (in the present preferred embodiment, the part exposed on the base surface 11B of the n.sup.−-type epitaxial layer 10) is at a position higher than that of the bottom portion of the source trench 33 and is contactable, said deepest portion may be at the same depth position as that of the bottom portion of the source trench 33 or may be deeper.

[0105] In the annular portion 37, an n.sup.+-type source region 32 and a p-type channel region 35 are formed in order from the base surface 11B side. Accordingly, the n.sup.+-type source region 32 and the p-type channel region 35 form parts of the side face of the gate trench 8, respectively. The n.sup.+-type source region 32 is, in the present preferred embodiment, formed with the same depth as that of the n.sup.+-type region 21 (refer to FIG. 3 to FIG. 6) and the p.sup.+-type channel contact region 34.

[0106] Also, in the n.sup.−-type epitaxial layer 10, a p-type layer 38 (for example, having a concentration of 1×10.sup.16 to 1×10.sup.19cm.sup.−3) is formed in a manner continuing from the p-type channel region 35 and the p.sup.+-type channel contact region 34 and the p-type layer 22 (refer to FIG. 4 to FIG. 6) described above. The p-type layer 38 is formed in a manner extending across the prismatic portion 36 and the annular portion 37 via the bottom portion of the source trench 33, and its inner region is in contact with the source trench 33 (exposed into the source trench 33). The p-type layer 38 is connected to the p-type channel region 35 at a portion lateral to the source trench 33 of the annular portion 37, and is connected to the p.sup.+-type channel contact region 34 at a portion lateral to the source trench 33 of the prismatic portion 36. Thus, the p-type channel region 35 and the p.sup.+-type channel contact region 34 are electrically connected via the p-type layer 38.

[0107] Also, the p-type layer 38 is also formed in a manner extending across outer peripheral edges of the outer trench 14 via a bottom portion of the outer trench 14, and is connected, at the outer peripheral edges, to the p-type well 19 extending to the outer peripheral portion 3. Also, the p-type layer 38 may be, as shown in FIG. 2 and FIG. 4, in the inner trench 13, formed only in crossing portions of the lines that constitute the inner trench 13. In addition, the crossing portions of the inner trench 13 correspond to corner portions of each unit cell 9, and no channel is formed there at ON-time, or if formed, a small current flows through the channel. Thus, even if the p-type layer 38 is formed in said crossing portions in a manner connected to the p-type channel region 35, there is virtually no influence on the device performance.

[0108] Also, the p-type layer 38 is, similar to the p-type layer 22, at bottom portions of the gate trench 8 and the source trench 33, formed to be thicker than a part at a side portion of the source trench 33. However, in the prismatic portion 36, a portion lateral to the source trench 33 is surrounded by the source trench 33, and ion implantation is uniformly performed from its periphery. Therefore, the p-type layer 38 is formed thicker than the part at the bottom portion of the source trench 33, so as to fill a part under the p.sup.+-type channel contact region 34.

[0109] Also, the p-type layer 38 is, in the present preferred embodiment, in a part other than the crossing portions of the inner trench 13 and the outer trench 14, formed across the entire periphery of the annular portion 37 surrounded by the gate trench 8, in a manner not contacting the gate trench 8 (spaced apart from the gate trench 8). Accordingly, an n.sup.−-type drain region 20 is disposed at a part of the side face of the gate trench 8 in each unit cell 9, so that a current path at the time of channel formation can be secured.

[0110] The gate trench 8 is, in the present preferred embodiment, formed in a substantially U-shape in a sectional view having a side face and a bottom face. On an inner surface (side face and bottom face) of the gate trench 8, a gate insulating film 17 is formed such that its one surface and the other surface extend along the inner surface of the gate trench 8.

[0111] The gate insulating film 17 is, at the bottom portion of the gate trench 8, formed to be thicker than a part at a side portion of the gate trench 8. In the gate trench 8 having a substantially U-shape in a sectional view as in the present preferred embodiment, the relatively thick part of the gate insulating film 17 is a part that contacts the bottom face of the gate trench 8, and the relatively thin part is a part that contacts the side face of the gate trench 8. By making the insulating film thick at the bottom portion of the gate trench 8 where electric field concentration is likely to occur, withstand voltage in the bottom portion of the gate trench 8 can be improved. In addition, the side face and bottom face sometimes cannot be clearly distinguished depending on the shape of the gate trench 8, but in that case, it suffices that the gate insulating film 17 that contacts a face in a direction crossing the depth direction of the gate trench 8 is relatively thick.

[0112] Moreover, the inside of the gate insulating film 17 is filled back with a gate electrode 16. In the present preferred embodiment, the gate electrode 16 is buried in the gate trench 8 such that its upper face becomes substantially flush with the base surface 11B of the n.sup.−-type epitaxial layer 10. The gate electrode 16 is opposed to the p-type channel region 35 via the gate insulating film 17. In each unit cell 9, by controlling a voltage to be applied to the gate electrode 16, an annular channel along the periphery of the unit cell 9 is formed in the p-type channel region 35. Then, a drain current that flows along the side face of the gate trench 8 toward the base surface 11B of the n.sup.−-type epitaxial layer 10 can be caused to flow to the n.sup.+-type source region 32 via the channel. A transistor operation of the semiconductor device 1 is thereby performed.

[0113] Similarly, the source trench 33 is also, in the present preferred embodiment, formed in a substantially U-shape in a sectional view having a side face and a bottom face. On an inner surface (side face and bottom face) of the source trench 33, a source trench insulating film 39 is formed such that its one surface and the other surface extend along the inner surface of the source trench 33.

[0114] The source trench insulating film 39 is, at the bottom portion of the source trench 33, formed to be thicker than a part at a side portion of the source trench 33. In addition, the side face and bottom face sometimes cannot be clearly distinguished depending on the shape of the source trench 33, but in that case, it suffices that the source trench insulating film 39 that contacts a face in a direction crossing the depth direction of the source trench 33 is relatively thick. Moreover, the inside of the source trench insulating film 39 is filled back with a trench buried layer 40. In the present preferred embodiment, the trench buried layer 40 is buried in the source trench 33 such that its upper face becomes substantially flush with the base surface 11B of the n.sup.−-type epitaxial layer 10.

[0115] In the present preferred embodiment, the gate insulating film 17 and the source trench insulating film 39 are constituted of the same material, and the gate electrode 16 and the trench buried layer 40 are constituted of the same material.

[0116] For example, as the material for the gate insulating film 17 and the source trench insulating film 39, a film of any of SiO.sub.2, AlON, Al.sub.2O.sub.3, SiO.sub.2/AlON, SiO.sub.2/AlON/SiO.sub.2, SiO.sub.2/SiN, and SiO.sub.2/SiN/SiO.sub.2 can be used, and more preferably, a film having a SiO.sub.2 film containing nitrogen (N) is used. In addition, SiO.sub.2/AlON means a laminated film of SiO.sub.2 (lower side) and AlON (upper side). Providing a gate insulating film 17 constituted of a high-dielectric-constant (high-k) film of AlON, Al.sub.2O.sub.3, or the like allows an improvement in gate withstand voltage, so that device reliability can be improved. Further, providing a gate insulating film 17 constituted of a material having a SiO.sub.2 film containing nitrogen (N) also allows an improvement in channel mobility.

[0117] As the material for the gate electrode 16 and the trench buried layer 40, polysilicon can be used, and more preferably, n.sup.+-type polysilicon is used. The n.sup.+-type polysilicon has a relatively low sheet resistance, which therefore allows increasing transistor switching speed.

[0118] In addition, the gate insulating film 17 and the source trench insulating film 39 may be constituted of materials different from each other. The gate electrode 16 and the trench buried layer 40 may also be similarly constituted of materials different from each other.

[0119] The contact holes 29 formed in the surface insulating film 26 selectively expose the source trench 33 and the n.sup.+-type source region 32 over the entire surface of the n.sup.−-type epitaxial layer 10. In the present preferred embodiment, a source portion 41 is defined in each unit cell 9 by the contact hole 29.

[0120] Next, a method for manufacturing the semiconductor device 1 described in FIG. 1 to FIG. 7 will be described.

[0121] For manufacturing the semiconductor device 1, an n-type impurity is doped into the surface of a SiC substrate (not shown) while SiC crystals are caused to grow thereon by epitaxy such as a CVD method, an LPE method, or an MBE method. An n.sup.−-type epitaxial layer 10 is thereby formed on the SiC substrate. A growth surface of the n.sup.−-type epitaxial layer 10 formed this time corresponds to the base surface 11B. In addition, as the n-type impurity, for example, N (nitride), P (phosphorous), As (arsenic), or the like can be used.

[0122] Next, a p-type impurity is selectively ion-implanted from the base surface 11B of the n.sup.−-type epitaxial layer 10. A p-type well 19 (p-type channel region 35) is thereby formed. In addition, as the p-type impurity, for example, Al (aluminum), B (boron), or the like can be used. Also, simultaneously with formation of the p-type well 19, the rest of the n.sup.−-type epitaxial layer 10 is formed as an n.sup.−-type drain region 20.

[0123] Next, an n-type impurity is selectively ion-implanted from the base surface 11B of the n.sup.−-type epitaxial layer 10. An n.sup.+-type region 21 and an n.sup.+-type source region 32 are thereby simultaneously formed.

[0124] Next, the n.sup.−-type epitaxial layer 10 is selectively etched by use of a mask having openings in regions where the gate trench 8, the source trenches 33, and the low step portion 12 are to be formed. The n.sup.−-type epitaxial layer 10 is thereby selectively dry-etched so that a gate trench 8, source trenches 33, and a low step portion 12 are formed, and simultaneously, a lower surface 11L is formed. In conjunction therewith, the n.sup.−-type epitaxial layer 10 is defined into a plurality of unit cells 9 by the gate trench 8. The unit cells 9 are to have prismatic portions 36 and annular portions 37. As an etching gas, for example, a mixed gas (SF.sub.6/O.sub.2 gas) containing SF.sub.6 (sulfur hexafluoride) and O.sub.2 (oxygen), a mixed gas (SF.sub.6/O.sub.2/HBr gas) containing SF.sub.6, O.sub.2, and HBr (hydrogen bromide), or the like can be used.

[0125] In addition, when locating the lower surface 11L of the outer peripheral portion 3 at a position deeper than the depth of the gate trench 8, it suffices to further selectively etch the low step portion 12 after the aforementioned etching.

[0126] Next, a p-type impurity is selectively ion-implanted from the semiconductor surface 11 of the n.sup.−-type epitaxial layer 10. The p-type impurity is implanted, for example, in a direction perpendicular to semiconductor surface 11 of the n.sup.−-type epitaxial layer 10. A p-type layer 22, a p-type layer 23, a p-type layer 38, and p-type guard rings 25 are thereby simultaneously formed. In addition, these layers 22, 23, 38, and 25 may be formed by separate ion implantation steps.

[0127] Next, a p-type impurity is selectively ion-implanted from the semiconductor surface 11 of the n.sup.−-type epitaxial layer 10. P.sup.+-type channel contact regions 34 and a p.sup.+-type well contact region 24 are thereby simultaneously formed.

[0128] Next, the n.sup.−-type epitaxial layer 10 is thermally treated at 1400° C. to 2000° C., for example. The ions of the p-type impurity and n-type impurity implanted into the n.sup.−-type epitaxial layer 10 are thereby activated.

[0129] Next, a gate insulating film 17 and a source trench insulating film 39 are simultaneously formed by, for example, thermal oxidization. In addition, when the gate insulating film 17 and the source trench insulating film 39 are constituted of high-dielectric-constant (high-k) films, it suffices to deposit a film material by a CVD method.

[0130] Next, a polysilicon material doped with an n-type impurity is deposited from above the n.sup.−-type epitaxial layer 10 by, for example, a CVD method. The deposition of the polysilicon material is continued until at least the gate trench 8 and the source trenches 33 have been completely filled back. Thereafter, by the deposited polysilicon material being patterned, the polysilicon material out of the gate trench 8 (inner trench 13 and outer trench 14) and out of the source trenches 33 is removed in the cell portion 2, and in the outer peripheral portion 3, the polysilicon material remains as an overlappingportion 18. At this time, the polysilicon material buried in the low step portion 12 is completely removed. A gate electrode 16 and a trench buried layer 40 are thereby simultaneously formed.

[0131] Next, an insulating material such as SiO.sub.2 is deposited from above the n.sup.−-type epitaxial layer 10 by, for example, a CVD method. A surface insulating film 26 is thereby formed.

[0132] Next, a part on the cell portion 2 of the surface insulating film 26 is selectively etched. Only said part is thereby thinned, so that an inner part 27 and an outer part 28 of the surface insulating film 26 are formed.

[0133] Next, by the surface insulating film 26 being selectively etched, contact holes 29 to 31 are simultaneously formed.

[0134] Next, a metal material is deposited from above the n.sup.−-type epitaxial layer 10 by, for example, a sputtering method. Then, by patterning said material, a source pad 4, a gate pad 5, and gate fingers 6 are simultaneously formed. The semiconductor device 1 shown in FIG. 1 to FIG. 7 is obtained through the above steps.

[0135] As above, according to the present semiconductor device 1, the semiconductor surface 11 in which the p-type layer 23 and the p-type guard rings 25 are formed serves as the lower surface 11L at a depth position equivalent to or deeper than the depth of the gate trench 8. The thickness of the n.sup.−-type epitaxial layer 10 from the bottom portion of the gate trench 8 to a back surface of the n.sup.−-type epitaxial layer 10 can thereby be made thicker than the thickness from the p-type layer 23 and the p-type guard rings 25 to said back surface. As a result, an electric field imposed on a section between the surface side and back surface side of the n.sup.−-type epitaxial layer 10 can be made to be stably shared by the p-type layer 23 and the p-type guard rings 25 of the outer peripheral portion 3. Because a stable electric field distribution can accordingly be formed in the n.sup.−-type epitaxial layer 10 without depending on the depth of the gate trench 8, an electric field concentration to the bottom portion of the gate trench 8 can be satisfactorily relaxed.

[0136] Also, as shown in FIG. 2, the gate trench 8 is formed in a region under the gate fingers 6, but the line-shaped contact trenches 15 are only formed in a manner running across the gate fingers 6, and moreover, the terminal portions of the contact trenches 15 are disposed further outside than the gate fingers 6. In other words, because trench corner portions (for example, corners etc., in the crossing portions of the inner trench 13) where an electric field is likely to concentrate when a gate voltage is applied are not disposed under the gate fingers 6, the reliability and resistance of the gate insulating film 17 can be improved.

[0137] Also, as shown in FIG. 7, the p-type layer 38 is also formed in a manner extending across the outer peripheral edges of the outer trench 14 via the bottom portion of the outer trench 14. A depletion layer can thereby be generated from a junction (p-n junction) between the p-type layer 38 and the n.sup.−-type epitaxial layer 10 (n.sup.−-type drain region 20). Moreover, because the depletion layer keeps equipotential surfaces away from the outer trench 14, electric fields to be imposed on the bottom portion of the outer trench 14 can be relaxed. Breakdown in the bottom portion of the outer trench 14 can accordingly be prevented.

[0138] Also, as shown in FIG. 5 and FIG. 6, in a region under the gate fingers 6, the n.sup.+-type region 21 is formed in the semiconductor surface 11 (base surface 11B) of the n.sup.−-type epitaxial layer 10. Because an n.sup.+-type semiconductor region has a higher oxidation rate than that of an n.sup.−-type semiconductor region, in a region under the gate fingers 6, a thick oxide film can be selectively formed in an upper portion of the gate trench 8 (contact trench 15) when the gate insulating film 17 is formed by thermal oxidization. An electric field to be imposed on an upper edge of the contact trench 15 when a gate voltage is applied can thereby be weakened to prevent a dielectric breakdown of the gate insulating film 17.

[0139] Also, as shown in FIG. 3 and FIG. 4, by selectively thinning the surface insulating film 26 (inner part 27) of the cell portion 2, a difference in level (unevenness) between the semiconductor surface 11 (device surface) in the source portions 41 within the contact holes 29 and a surface of the surface insulating film 26 can be reduced. When a source pad 4 is buried in the contact holes 29 to form a source pad 4 on the surface insulating film 26, the flatness of the source pad 4 can thereby be further improved.

[0140] On the other hand, the thickness of the surface insulating film 26 (outer part 28) of the outer peripheral portion 3 can be designed separately from the thickness of the inner part 27. Thus, designing with such a thickness so as not to influence the electric field distribution in the outer peripheral portion 3 allows maintaining breakdown characteristics. In other words, according to this arrangement, at the time of an improvement in flatness of the source pad 4, variation in breakdown characteristics and a dielectric breakdown failure due to the variation can be prevented.

[0141] Also, as shown in FIG. 7, the trench buried layer 40 is buried in the source trenches 33 via the trench insulating film 39. Therefore, on the surface of the n.sup.−-type epitaxial layer 10 (device surface), a difference in level (unevenness) between the source portions 41 exposed from the contact holes 29 and other parts can be reduced. The flatness of the source pad 4 on said device surface can thereby be improved. Thus, when, for example, a wire is bonded to the surface of the source pad 4, adhesion between the source pad 4 and the wire can be improved. As a result, the wire can be satisfactorily bonded, so that the wire bonding portion can be improved in reliability. Further, because the source pad 4 is excellent in flatness, destruction of the device by ultrasonic vibration and pressure can be prevented at the time of wire bonding, and a decline in assembling yield can be prevented.

[0142] On the other hand, a concentration of equipotential surfaces in a vicinity of the bottom portion of the gate trench 8 can be prevented by the source trench 33, so that a potential gradient in the vicinity of the bottomportion can be made gradual. Therefore, an electric field concentration to the bottom portion of the gate trench 8 can be relaxed. Further, the p.sup.+-type channel contact region 34 is formed in the top portion of the prismatic portion 36 and is disposed at a position higher than that of the bottom portion of the source trench 33. Thus, even when there is formed a source trench 33, contact with the p-type channel region 35 can be reliably made via the p.sup.+-type channel contact region 34. In other words, at the time of an improvement in flatness of the source pad 4, a degradation in device performance such as gate withstand voltage and contact performance with the p-type channel region 35 can be prevented.

[0143] Further, in the present preferred embodiment, because the p-type layer 38 is formed around the source trench 33, a depletion layer can be generated from a junction (p-n junction) between the p-type layer 38 and the n.sup.−-type drain region 20. Moreover, because the depletion layer keeps equipotential surfaces away from the gate trench 8, electric fields to be imposed on the bottom portion of the gate trench 8 can be further relaxed.

[0144] Also, in the present preferred embodiment, because a SiC device in which latch-up is unlikely to occur as compared with a Si device is used, the p.sup.+-type channel contact region 34 and the p-type channel region 35 can be provided at positions separated from each other by the source trench 33. That is, in a Si device, because latch-up is relatively likely to occur, it is preferable to dispose the p.sup.+-type channel contact region 34 near the p-type channel region 35 to reduce the distance between the regions 34 and 35 as short as possible so as to lower a base resistance between said regions 34 and 35. On the other hand, in such a SiC device as the present semiconductor device 1, because latch-up is relatively unlikely to occur and the importance of considering a base resistance between the regions 34 and 35 is low, the p.sup.+-type channel contact region 34 does not need to be disposed near the p-type channel region 35. Thus, the p.sup.+-type channel contact region 34 and the p-type channel region 35 can be provided at positions separated from each other by the source trench 33 to electrically connect the regions 34 and 35 by a route through the bottom portion of the source trench 33.

[0145] Also, because the source trench insulating film 39 is disposed outside of the trench buried layer 40, flow of an off-leakage current between the n.sup.−-type epitaxial layer 10 and the source pad 4 can be prevented. Specifically, the p-type layer 38 is, at a side portion of the source trench 33, thinner than a part at the bottom portion of the source trench 33 because ions are unlikely to enter a portion lateral to the source trench 33 at the time of ion implantation. Therefore, when a high voltage is applied at OFF-time, an off-leakage current may flow passing through the thin part of the p-type layer 38. Therefore, forming a source trench insulating film 39 allows reliably interrupting a leakage current by the source trench insulating film 39 even if an off-leakage current passes through the p-type layer 38.

[0146] Also, if the trench buried layer 40 buried in the source trench 33 is polysilicon, when forming contact holes 29 in the surface insulating film 26 made of SiO.sub.2, the trench buried layer 40 (polysilicon layer) can be used as an etching stopper. Therefore, control of the step of said contact etching can be simplified.

[0147] Also, because the source trenches 33 are formed simultaneously with the gate trench 8, the source trenches 33 can be simply formed free from misalignment without increasing the manufacturing process. Further, if the source trenches 33 and the gate trench 8 are the same width, the etching rate for the source trenches 33 can be made the same as that for the gate trench 8, so that etching for forming the source trenches 33 can be stably controlled.

[0148] Next, modifications of the cell portion 2 will be described with reference to FIG. 8 to FIG. 12.

[0149] FIG. 8 to FIG. 12 are views showing first to fifth modifications of the cell portion 2. In FIG. 8 to FIG. 12, parts corresponding to the respective portions shown in FIG. 7 described above are shown with the same reference signs.

[0150] In the form of FIG. 7, the trench buried portion buried in the source trench 33 consists of the source trench insulating film 39 and the trench buried layer 40 (polysilicon layer), but as shown in FIG. 8, it may consist only of an insulating layer 42 that fills back the source trenches 33.

[0151] As the material for the insulating layer 42, SiO.sub.2 can be used, and more preferably, SiO.sub.2 containing phosphorus (P) or boron (B) is used. As such SiO.sub.2, for example, PSG (phosphorus silicate glass) or PBSG (phosphorus boron silicate glass) can be used.

[0152] A process for manufacturing the semiconductor device of the form shown in FIG. 8 is substantially the same as the steps described in the foregoing. However, after a gate electrode 16 and a trench buried layer 40 are formed, the trench buried layer 40 is selectively etched to be removed, so that the source trenches 33 are made hollow. Then, a surface insulating film 26 is formed on the n.sup.−-type epitaxial layer 10 to thereby fill back the source trenches 33 by use of a part of the surface insulating film 26. The source trench insulating film 39 and the surface insulating film 26 are thereby integrated inside the source trenches 33, so that an insulating layer 42 is formed.

[0153] According to this arrangement, because the source trenches 33 are filled with the insulating layer 42, flow of an off-leakage current between the n.sup.−-type epitaxial layer 10 and the source pad 4 can be effectively prevented.

[0154] Also, if the insulating layer 42 is SiO.sub.2 containing phosphorous or boron, because the melting point of SiO.sub.2 falls, the process for burying the insulating layer 42 can be simplified.

[0155] Also, as shown in FIG. 9, the trench filling portion buried in the source trench 33 may consist only of a polysilicon layer 43 that fills back the source trenches 33. As the material for the polysilicon layer 43, p.sup.+-type polysilicon is preferably used.

[0156] A process for manufacturing the semiconductor device of the form shown in FIG. 9 is substantially the same as the steps described in the foregoing. However, after a gate insulating film 17 and a source trench insulating film 39 are formed, the source trench insulating film 39 is selectively etched to be removed, so that the source trenches 33 are made hollow. Then, by polysilicon being deposited from above the n.sup.−-type epitaxial layer 10, the source trenches 33 are filled back with that polysilicon. A gate electrode 16 and a polysilicon layer 43 are thereby simultaneously formed.

[0157] According to this arrangement, because the polysilicon layer 43 is buried in the source trenches 33, when forming contact holes 29 in the surface insulating film 26 made of SiO.sub.2, the polysilicon layer 43 can be used as an etching stopper. Therefore, control of the step of said contact etching can be simplified.

[0158] Also, if the polysilicon layer 43 is p.sup.+-type polysilicon, the p.sup.+-type channel contact region 34 andthep-type channel region 35 can be electrically connected by use of the polysilicon layer 43. Because the length of a current path between the regions 34 and 35 can thereby be reduced, a base resistance therebetween can be reduced. As a result, latch-up can be satisfactorily prevented. Further, because the p.sup.+-type channel contact region 34 is in contact with the polysilicon layer 43 at a side face of the source trench 33, a contact resistance therebetween can also be reduced. The reduction in contact resistance also contributes to a reduction in the base resistance between the regions 34 and 35.

[0159] Also, in the form of FIG. 7, the source trench 33 is formed in an annular shape in a region surrounded by the annular n.sup.+-type source region 32, but as shown in FIG. 10, a source trench 44 in a recessed shape showing a quadrangular shape in a plan view may be formed in a region surrounded by the n.sup.+-type source region 32. In this case, a p.sup.+-type channel contact region 45 may be formed in a surface portion of the p-type layer 38 at a bottom portion of the source trench 44.

[0160] Also, in the form of FIG. 7, the gate electrode 16 is a layer made only of polysilicon that fills back the inside of the gate insulating film 17, but as shown in FIG. 11, it may consist of a base film 46 made of polysilicon formed, on the gate insulating film 17, such that its one surface and the other surface extend along the inner surface of the gate trench 8 and a buried metal 47 containing at least one of Mo, W, Al, Pt, Ni, and Ti buried inside of the base film 46. In this case, the trench buried portion within the source trench 33 may also similarly consist of a base film 48 made of polysilicon formed, on the source trench insulating film 39, such that its one surface and the other surface extend along the inner surface of the source trench 33 and a buried metal 49 made of the same material as that for the buried metal 47 buried inside of the base film 48.

[0161] According to this arrangement, a metal gate using the buried metal 47 can make gate resistance relatively low as compared with that of a polysilicon gate, which therefore allows increasing transistor switching speed.

[0162] Also, a trench-gate type structured MISFET is formed in the cell portion 2 of FIG. 7, but as shown in FIG. 12, a planar type structured MISFET may be formed in the cell portion 2.

[0163] That is, in the form shown in FIG. 12, p-type wells 19 are arrayed in a matrix shape (in an array) in the cell portion 2 in a manner corresponding to the respective unit cells 9. In a surface portion of each p-type well 19, an annular n.sup.+-type source region 50 is formed in a manner exposed on the base surface 11B. Moreover, a gate electrode 51 is disposed via a gate insulating film 52 in a manner opposed to a region between an outer peripheral edge of each p-type well 19 and an outer peripheral edge of the n.sup.+-type source region 50. The surface insulating film 26 covers the gate electrode 51.

Second Preferred Embodiment

[0164] FIG. 13 and FIG. 14 are schematic sectional views of a semiconductor device according to a second preferred embodiment of the present invention, and show sectional structures corresponding to FIG. 3 and FIG. 4, respectively. In FIG. 13 and FIG. 14, parts corresponding to the respective portions shown in FIG. 3 and FIG. 4 described above are shown with the same reference signs.

[0165] In the first preferred embodiment described above, a boundary between the base surface 11B and the lower surface 11L due to the low step portion 12 is set further inside than a contact position of the source pad 4 with respect to the p-type well 19 extending across the cell portion 2 and the outer peripheral portion 3, but as shown in FIG. 13 and FIG. 14, it may be set outside. In this case, the p.sup.+-type well contact region 24 is formed at a position spaced apart to the outside with respect to the n.sup.+-type region 21 in an inner region of the p-type well 19.

[0166] According to this arrangement, both the p.sup.+-type channel contact regions 34 and the p.sup.+-type well contact region 24 can be formed in the base surface 11B, which can therefore make mask alignment easy at the time of ion injection when these regions 24 and 34 are formed. Of course, the same effects as those of the first preferred embodiment can also be realized.

Third Preferred Embodiment

[0167] FIG. 15 and FIG. 16 are schematic sectional views of a semiconductor device according to a third preferred embodiment of the present invention, and show sectional structures corresponding to FIG. 3 and FIG. 4, respectively. In FIG. 15 and FIG. 16, parts corresponding to the respective portions shown in FIG. 3 and FIG. 4 described above are shown with the same reference signs.

[0168] In the first preferred embodiment described above, the low step portion 12 is formed in the outer peripheral portion 3, but in the present third preferred embodiment, no low step portion 12 is formed in the outer peripheral portion 3, and the outer peripheral portion 3 has a semiconductor surface 11 at the same height position as that of the base surface 11B of the cell portion 2.

[0169] According to this arrangement, both the p.sup.+-type channel contact regions 34 and the p.sup.+-type well contact region 24 can be formed in the base surface 11B, which can therefore make mask alignment easy at the time of ion injection when these regions 24 and 34 are formed. Of course, the same effects as those of the first preferred embodiment can also be realized.

First Reference Embodiment

[0170] FIG. 17 and FIG. 18 are schematic sectional views of a semiconductor device according to a first reference embodiment of the present invention, and show sectional structures corresponding to FIG. 3 and FIG. 4, respectively. In FIG. 17 and FIG. 18, parts corresponding to the respective portions shown in FIG. 3 and FIG. 4 described above are shown with the same reference signs.

[0171] In the first preferred embodiment described above, the surface insulating film 26 is formed such that the inner part 27 on the cell portion 2 becomes thinner than the outer part 28 on the outer peripheral portion 3, but as shown in FIG. 17 and FIG. 18, it may be formed such that the inner part 27 on the cell portion 2 has the same thickness as that of the outer part 28 on the outer peripheral portion 3. The film thickness may be, for example, about 5500 Å to 20000 Å.

Second Reference Embodiment

[0172] FIG. 19 and FIG. 20 are schematic sectional views of a semiconductor device according to a second reference embodiment of the present invention, and show sectional structures corresponding to FIG. 3 and FIG. 4, respectively. In FIG. 19 and FIG. 20, parts corresponding to the respective portions shown in FIG. 3 and FIG. 4 described above are shown with the same reference signs.

[0173] The structure in FIG. 19 and FIG. 20 is an example for which the arrangement of the surface insulating film 26 having a uniform thickness of the first reference embodiment described above is combined with the structure of the second preferred embodiment.

Fourth Preferred Embodiment

[0174] FIG. 21 is a schematic sectional view of a semiconductor device according to a fourth preferred embodiment of the present invention, and shows a sectional structure corresponding to FIG. 3. In FIG. 21, parts corresponding to the respective portions shown in FIG. 3 described above are shown with the same reference signs.

[0175] In the first preferred embodiment described above, the voltage resistant structure of the outer peripheral portion 3 consists only of p-type semiconductor regions, like the p-type layer 23 and the p-type guard rings 25, but as shown in FIG. 21, it may be arranged to include a trench formed in the lower surface 11L and a p-type semiconductor region formed at a bottom portion of the trench. In this case, the trench may have a conductive material buried therein via an insulating film. In the present preferred embodiment, guard rings 55 are formed each including a trench 53 formed in the lower surface 11L and having an annular shape to surround the cell portion 2 and a p-type layer 54 which is formed at bottom and side portions of the trench 53 and an inner region of which is in contact with the trench 53. In the trenches 53, a polysilicon layer 57 is buried via a trench insulating film 56.

[0176] By this arrangement as well, the same effects as those of the first preferred embodiment can be realized.

[0177] Although preferred embodiments of the present invention have been described above, the present invention can be embodied in other forms.

[0178] For example, an arrangement may be adopted in which the conductivity type of each semiconductor part of the semiconductor device 1 is inverted. For example, in the semiconductor device 1, the p-type parts may be n-type and the n-type parts may be p-type.

[0179] Also, in the semiconductor device 1, the layer that constitutes a semiconductor layer is not limited to an n.sup.−-type epitaxial layer made of SiC, and may be a layer or the like made of GaN, diamond, or Si.

[0180] Also, each unit cell 9 is not limited to a square shape in a plan view (quadrangular shape), but may have another shape such as, for example, a triangular shape in a plan view, a pentagonal shape in a plan view, or a hexagonal shape in a plan view.

[0181] The semiconductor device of the present invention can be incorporated in, for example, a power module for use in an inverter circuit that constitutes a drive circuit for driving an electric motor available as a power source for an electric vehicle (including a hybrid vehicle), an electric train, an industrial robot, and the like. Additionally, the semiconductor device of the present invention can also be incorporated in a power module for use in an inverter circuit that converts electric power generated by a solar cell, a wind power generator, and other power generators (particularly, private electric generators) so as to be matched with electric power from commercial power sources.

[0182] Also, the features grasped from the disclosures of the preferred embodiments described above may be combined with each other even among different preferred embodiments. Also, the components presented in the respective preferred embodiments may be combined within the scope of the present invention.

[0183] The preferred embodiments of the present invention are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be interpreted as being limited to these specific examples, and the spirit and scope of the present invention shall be limited solely by the accompanying claims.

[0184] The present application corresponds to Japanese Patent Application No. 2013-43407 filed on Mar. 5, 2013 in the Japan Patent Office, and the entire disclosure of this application is incorporated herein by reference.

REFERENCE SIGNS LIST

[0185] 1 Semiconductor device

[0186] 2 Cell portion

[0187] 3 Outer peripheral portion

[0188] 4 Source pad

[0189] 5 Gate pad

[0190] 6 Gate finger

[0191] 7 Removal region

[0192] 8 Gate trench

[0193] 9 Unit cell

[0194] 10 N.sup.−-type epitaxial layer

[0195] 11 Semiconductor surface

[0196] 11B Base surface

[0197] 11L Lower surface

[0198] 12 Low step portion

[0199] 13 Inner trench

[0200] 14 Outer trench

[0201] 15 Contact trench

[0202] 16 Gate electrode

[0203] 17 Gate insulating film

[0204] 18 Overlapping portion

[0205] 19 P-type well

[0206] 20 N.sup.−-type drain region

[0207] 21 N.sup.+-type region

[0208] 22 P-type layer

[0209] 23 P-type layer

[0210] 24 P.sup.+-type well contact region

[0211] 25 P-type guard ring

[0212] 26 Surface insulating film

[0213] 27 Inner part

[0214] 28 Outer part

[0215] 29 Contact hole

[0216] 30 Contact hole

[0217] 31 Contact hole

[0218] 32 N.sup.+-type source region

[0219] 33 Source trench

[0220] 34 P.sup.+-type channel contact region

[0221] 35 P-type channel region

[0222] 36 Prismatic portion

[0223] 37 Annular portion

[0224] 38 P-type layer

[0225] 39 Source trench insulating film

[0226] 40 Trench buried layer

[0227] 41 Source portion

[0228] 42 Insulating layer

[0229] 43 Polysilicon layer

[0230] 44 Source trench

[0231] 45 P.sup.+-type channel contact region

[0232] 46 Base film

[0233] 47 Buried metal

[0234] 48 Base film

[0235] 49 Buried metal

[0236] 50 N.sup.+-type source region

[0237] 51 Gate electrode

[0238] 52 Gate insulating film

[0239] 53 Trench

[0240] 54 P-type layer

[0241] 55 Guard ring

[0242] 56 Trench insulating film

[0243] 57 Polysilicon layer