Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

A semiconductor device includes a third electrode between a first semiconductor region and a second electrode, a fourth electrode between the first semiconductor region and the second electrode, a second semiconductor region between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth electrode between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and a fifth semiconductor region between the first electrode and the first semiconductor region. A first insulating film is provided between the third electrode and the first semiconductor region, the second semiconductor region, the third semiconductor region and the second electrode. A second insulating film is provided between the fourth semiconductor region and the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.

A semiconductor device includes first and second electrodes and a silicon carbide layer located between the first and second electrodes. A plurality of gate electrodes is interposed between the first electrode and the silicon carbide layer and extends in a first direction. The silicon carbide layer includes a plurality of spaced apart openings having sidewalls and a base which extend inwardly between the gate electrodes, a first region containing a second conductivity type impurity extending around and under the openings, and a second region containing a second conductivity type impurity interposed between the portion of the first region extending under the base of the openings. The concentration of the second conductivity type impurity is greater in the second region than in the first region. The silicon carbide layer includes a third region containing a first conductivity type impurity extending inwardly of the first region from the sidewall of the openings.

A semiconductor device includes a first source region, a second source region, and a drain region. The first source region includes a first conductivity type that is formed in a semiconductor layer. The second source region includes a second conductivity type that is adjacent to a gate region and formed in the first source region, the second source region being electrically connected to the first source region, and configured such that one end of a first face of the second source region abuts a gate insulating film formed in the gate region and at least a portion of a second face opposite to the first face abuts the first source region. The drain region includes the first conductivity type that is formed adjacent to the gate region in the semiconductor layer with the gate region interposed with the second source region and the drain region.

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof

A silicon carbide semiconductor device includes a substrate, a drift layer disposed above the substrate, a base region disposed above the drift layer, a source region disposed above the base region, a gate trench formed deeper than the base region from a surface of the source region, a gate insulating film covering an inner wall surface of the gate trench, a gate electrode disposed on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film and having a contact hole, a source electrode brought in ohmic contact with the source region through the contact hole, and a drain electrode disposed to a rear surface of the substrate. The source region has a lower impurity concentration on a side close to the base region than on a surface side brought in ohmic contact with the source region.

Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Disclosed are a semiconductor device, a preparation method therefor and electrical equipment thereof. The semiconductor device includes: a silicon substrate on which an emitter, a gate, and a collector are formed; a bootstrap electrode formed on the silicon substrate; and an insulating layer, formed on the silicon substrate and disposed between the emitter and the bootstrap electrode. A bootstrap capacitor is formed between the emitter and the bootstrap electrode.

A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches.

Thyristor semiconductor device comprising an anode region, a first base region and a second base region having opposite types of conductivity, and a cathode region, all superimposed along a vertical axis.