A semiconductor device capable of suppressing the calorific value at the central portion of a wire bonding area is provided. A semiconductor device includes a plurality of IGBT cells in a cell area. An emitter electrode serves as a current path when a plurality of IGBT cells are in conductive state, and is formed to cover a plurality of IGBT cells. A wire is bonded to the emitter electrode. A dummy cell which does not perform a bipolar operation, is formed at least below a central portion of a wire bonding area which is an area at which the wire and the emitter electrode are bonded.

A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.

Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

Provided is a semiconductor device which includes a semiconductor substrate including a transistor portion and a diode portion. The transistor portion includes an injection suppression region that suppresses injection of a carrier of a second conductivity type at an end portion on the diode portion side in a top view of the semiconductor substrate. The diode portion includes a lifetime control region including a lifetime killer. Both the transistor portion and the diode portion include a base region of a second conductivity type on a surface of the semiconductor substrate, the transistor portion further includes an emitter region of a first conductivity type and an extraction region of a second conductivity type having a higher doping concentration than the base region on the surface of the semiconductor substrate, and the injection suppression region is not provided with the emitter region and the extraction region.

Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

A semiconductor device includes a semiconductor substrate including a drift region of a first conductivity type, a transistor portion provided in the substrate, and an adjacent element portion provided in the substrate, the adjacent element and transistor portions being arranged along an arrangement direction. The transistor and adjacent element portions both include a base region of a second conductivity type provided above the drift region, trench portions formed through the base region, extending in an extending direction orthogonal to the arrangement direction on the upper surface, and having a conducting portion therein, and a first lower surface side lifetime control region provided, on a lower surface side, continuously from the transistor portion to the adjacent element portion and includes a lifetime killer. The lifetime control region is provided over entirety of the transistor portion and in a part of the adjacent element portion in a top view of the substrate.

Provided is a semiconductor apparatus comprising: an emitter region having a first conductivity type provided on a front surface of a semiconductor substrate; a first gate trench part and a second gate trench part in contact with the emitter region; a first emitter non-contact trench part and a second emitter non-contact trench part out of contact with the emitter region; a gate pad for setting the first gate trench part, the second gate trench part, the first emitter non-contact trench part, and the second emitter non-contact trench part to gate potential; and a diode having an anode connected to the gate pad and a cathode connected to the first emitter non-contact trench part and the second emitter non-contact trench part, wherein the first gate trench part, the first emitter non-contact trench part, the second gate trench part, and the second emitter non-contact trench part are adjacently arranged in order.

An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer having a first n-type dopant, depositing a first portion of a second epitaxial layer having a second n-type dopant on the first epitaxial layer, implanting ions into the first portion of the second epitaxial layer to form a recombination region, depositing a second portion of the second epitaxial layer having the second n-type dopant on the recombination region, and forming trenches in the second portion of the second epitaxial layer, wherein the trenches comprise a trench gate of the transistor and a termination trench. The second portion of the second epitaxial layer is thicker than the first portion of the second epitaxial layer.

Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate.