A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.

Provided is a compound semiconductor device that can suppress the deterioration of the element characteristics and a method of manufacturing a compound semiconductor device. The compound semiconductor device includes a laminated body constituted of a compound semiconductor and including a channel layer in which a first conductivity type carrier runs; a gate electrode provided on an upper surface side of the laminated body; a source electrode provided on the upper surface side of the laminated body; and a drain electrode provided on the upper surface side of the laminated body. The laminated body includes a second conductivity type first low resistance layer that is provided at a position facing the gate electrode and is in contact with the gate electrode, a first electric-field relaxation layer extended from the first low resistance layer toward a side of one of the source electrode and the drain electrode and configured to relax electric field concentration to the first low resistance layer, and a first amorphous layer covering a first side surface that is a side surface of the first electric-field relaxation layer and faces one of the source electrode and the drain electrode.

A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

The present disclosure provides a GaN-based semiconductor structure, including: a substrate; a channel layer; a barrier layer, where the channel layer and the barrier layer each include a gate region, a source region and a drain region; a source region N-type ion heavily-doped layer located in the source region; a drain region N-type ion heavily-doped layer located in the drain region; a gate electrode located in the gate region; a source electrode located on the source region N-type ion heavily-doped layer; and a drain electrode located on the drain region N-type ion heavily-doped layer.

A field effect transistor comprising: a first semiconductor structure, the first semiconductor structure having a channel layer; a second semiconductor structure, the second semiconductor structure is arranged on the first semiconductor structure, and the second semiconductor structure is stacked in sequence from bottom to top with a Schottky layer, a first etch stop layer, a wide recess layer, an ohmic contact layer, and a narrow recess, a wide recess is opened in the ohmic contact layer, so that the upper surface of the wide recess layer forms a wide recess area and the upper surface of the Schottky layer forms a narrow recess area; at least one delta-doped layer, a gate metal contact, the gate metal contact is formed inside the wide recess a source metal contact; and a drain metal contact, and the drain metal contact is located on the other side of the gate metal contact.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.

A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.