A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.

A semiconductor device having a substrate and an orthorhombic polar crystalline oxide k-Al.sub.2O.sub.3 layer epitaxially and heterogeneously integrated above a wurtzite single-crystal Group III-Nitride layer comprising AlN disposed above the substrate.

A semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, a second dielectric layer disposed over the first dielectric layer, a third dielectric layer disposed over the second dielectric layer, a lower opening formed in the first dielectric layer, an upper opening formed in the second dielectric layer and the third dielectric layer, wherein at least a portion of the upper opening overlaps a portion of the lower opening, and a control electrode formed within at least a portion of the lower opening and within a portion of the upper opening, wherein a portion of the control electrode is formed over the third dielectric layer.

An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor substrate. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and the second current-carrying electrode. A conductive element formed over the first dielectric layer, adjacent the control electrode, and between the control electrode and the second current-carrying electrode, includes a first region formed a first distance from the upper surface of the semiconductor substrate and a second region formed a second distance from the upper surface of the semiconductor substrate. An insulating region is formed between the control electrode and the conductive element.

An insulated gate bipolar transistor includes a P-type group III-V nitride compound layer. An N-type group III-V nitride compound layer contacts a side of the P-type group III-V nitride compound layer. An HEMT is disposed on the N-type group III-V nitride compound layer. The HEMT includes a first group III-V nitride compound layer disposed on the N-type group III-V nitride compound layer. A second group III-V nitride compound layer is disposed on the first group III-V nitride compound layer. A source is embedded within the second group III-V nitride compound layer and the first group III-V nitride compound layer, wherein the source includes an N-type group III-V nitride compound body and a metal contact. A drain contacts another side of the P-type group III-V nitride compound layer. A gate is disposed on the second group III-V nitride compound layer.

A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.

A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge and a method of making the same is disclosed. The HEMT device includes a substrate with epitaxial layers over the substrate. An n-type gallium nitride (GaN) layer is disposed on an interface surface of the epitaxial layers, wherein the n-type GaN layer is co-doped with silicon (Si) and germanium (Ge) that provide a carrier concentration of at least 1×10.sup.20 cm.sup.−3 and a root mean square (RMS) surface roughness that is no greater than 2 nm for a contact surface of the n-type GaN layer that is interfaced with the interface surface of the epitaxial layers.

A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth substrate in the Ga-polar direction such that the support substrate faces the Ga-plane of the GaN epitaxial substrate. Furthermore, at least the growth substrate is removed from the GaN epitaxial substrate so as to expose an N-plane of the GaN epitaxial substrate. Subsequently, a semiconductor element is formed on the N-plane side.

A GaN epitaxial substrate comprises a growth substrate and a multilayer structure grown on the growth substrate in the Ga-polar direction. The multilayer structure comprises: a buffer layer, an n-type conductive layer formed on the buffer layer, a first GaN layer formed on the n-type conductive layer, an electron supply layer formed on the first GaN layer, and a second GaN layer formed on the electron supply layer.

Systems and method are provided for depositing metal on GaN transistors after gate formation using a metal nitride Schottky gate. Embodiments of the present disclosure use a “diamond last” process using thermally stable metal nitride gate electrodes to enable thicker heat spreading films and facilitate process integration. In an embodiment, the “diamond last” process with high thermal conductivity diamond is enabled by the integration of thermally stable metal-nitride gate electrodes.