Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1-x1-y1)(Al.sub.q1Ga.sub.1-q1).sub.2O.sub.4 wherein 0?x1?1, 0?y1?1 and 0?q1?1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1-x2-y2)(Al.sub.q2Ga.sub.1-q2).sub.2O.sub.4 wherein 0?x2?1, 0?y2?1 and 0?q2?1. In some cases, at least one condition selected from x1?x2, y1?y2, and q1?q2 is satisfied.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

Structures and methods for a tunnel field-effect transistor (TFET). The TFET includes a gate electrode, a source region having a first conductivity type, a drain region having a second conductivity type opposite from the first conductivity type, and a dielectric layer separating the gate electrode from the source region and the drain region. The dielectric layer provides a channel region between the source region and the drain region. The channel region includes a relatively thin tunnel dielectric between the source region and the gate electrode and a relatively thick drift dielectric between the gate electrode and the drain region.

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.