Aspects of the disclosure provide a bipolar transistor structure with an elevated extrinsic base, and related methods to form the same. A bipolar transistor according to the disclosure may include a collector on a substrate, and a base film on the collector. The base film includes a crystalline region on the collector and a non-crystalline region adjacent the crystalline region. An emitter is on a first portion of the crystalline region of the base film. An elevated extrinsic base is on a second portion of the crystalline region of the base film, and adjacent the emitter.

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.

A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.

An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

A semiconductor device includes a semiconductor substrate in which a first region having a freewheeling diode arranged therein, second regions having an IGBT arranged therein, and a withstand-voltage retention region surrounding the first region and the second regions in plan view are defined. The semiconductor substrate has a first main surface and a second main surface. The semiconductor substrate includes an anode layer having a first conductivity type, which is arranged in the first main surface of the first region, and a diffusion layer having the first conductivity type, which is arranged in the first main surface of the withstand-voltage retention region adjacently to the anode layer. A first trench is arranged in the first main surface on a side of the anode layer with respect to a boundary between the anode layer and the diffusion layer.

A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.

The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.