Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

Provided is a switch apparatus including a conductor; a switching device that contacts the conductor on a first surface and switches between a first terminal on the first surface side and a second terminal on a second surface side that is opposite to the first surface; and a control device that contacts the conductor on a third surface and includes a control circuit of the switching device provided on a fourth surface side opposite to the third surface and a first withstand voltage structure that protects the control circuit from excessive voltage added to the conductor. By providing the withstand voltage structure in the control device, it is possible to protect the control circuit.

A semiconductor device includes a third electrode between a first semiconductor region and a second electrode, a fourth electrode between the first semiconductor region and the second electrode, a second semiconductor region between the first semiconductor region and the second electrode and between the third electrode and the fourth electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth electrode between the first semiconductor region and the second electrode to be electrically connected to the second electrode, and a fifth semiconductor region between the first electrode and the first semiconductor region. A first insulating film is provided between the third electrode and the first semiconductor region, the second semiconductor region, the third semiconductor region and the second electrode. A second insulating film is provided between the fourth semiconductor region and the first semiconductor region, the second semiconductor region, and the fourth semiconductor region.

The present application discloses new approaches to providing “passive-off” protection for a B-TRAN-like device. Even if the control circuitry is inactive, AC coupling uses transient voltage on the external terminals to prevent forward biasing an emitter junction. Preferably the same switches which implement diode-mode and pre-turnoff operation are used as part of the passive-off circuit operation.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n.sup.− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p.sup.+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n.sup.+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×10.sup.15 cm.sup.−3 or more, and one-tenth or less of the peak impurity concentration of the p.sup.+ type collector layer, can be included between the n-type field-stop layer and p.sup.+ type collector layer.

A silicon carbide semiconductor device, including a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor deposition layer of the first conductivity type, deposited on a front surface of the silicon carbide semiconductor substrate and having an impurity concentration that is lower than that of the silicon carbide semiconductor substrate, a base region of a second conductivity type, selectively provided in the first silicon carbide semiconductor deposition layer at a front surface thereof, and a second silicon carbide semiconductor deposition layer of the second conductivity type, deposited on the front surface of the first silicon carbide semiconductor deposition layer. The base region has an impurity concentration of 1×10.sup.18 to 1×10.sup.20/cm.sup.3 and a thickness of 0.3 to 1.0 μm. The second silicon carbide semiconductor deposition layer has a surface defect density of 3 defects/cm.sup.2.

At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.

A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential.

Methods of fabricating ESD protection devices include forming a single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40 V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly-doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40 V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.