The present disclosure describes a semiconductor structure that includes a substrate from an undoped semiconductor material and a fin disposed on the substrate. The fin includes a non-polar top surface and two opposing first and second polar sidewall surfaces. The semiconductor structure further includes a polarization layer on the first polar sidewall surface, a doped semiconductor layer on the polarization layer, a dielectric layer on the doped semiconductor layer and on the second polar sidewall surface, and a gate electrode layer on the dielectric layer and the first polarized sidewall surface.

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

A display device includes: a substrate including a display area and a non-display area; a gate driver disposed on the substrate in the non-display area and including a plurality of stages that generate a gate signal and output the gate signal to the display area; a switching transistor and a driving transistor disposed on the substrate in the display area; and a light emitting diode connected to the driving transistor, wherein each of the plurality of stages may include a plurality of transistors, wherein a channel layer of the driving transistor includes a first oxide semiconductor material, and a channel layer of the plurality of transistors included in each of the plurality of stages includes a second oxide semiconductor material, wherein the first oxide semiconductor material is different from the second oxide semiconductor material, and wherein the second oxide semiconductor material may include tin.

A high output and high speed electronic device having low cost and high productivity is disclosed. The copper halide semiconductor based electronic device, includes a substrate, a copper halide channel layer formed on the substrate, an insulating layer formed on the copper halide channel layer, a gate electrode formed on the insulating layer, a first n+copper halide layer formed on the copper halide channel layer to be disposed at a first side of the gate electrode, the first n+copper halide layer comprising n-type impurities, a drain electrode formed on the first n+copper halide layer, a second n+copper halide layer formed on the copper halide channel layer to be disposed at a second side of the gate electrode, which is opposite to the first side, the second n+copper halide layer comprising n-type impurities, and a source electrode formed on the second n+copper halide layer.

A tunnel field effect transistor (TFET) device includes a substrate, heavily doped source and drain regions disposed at opposite ends of a channel region forming a PiN or NiP structure, the channel region including a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion having a second length defined along the longitudinal axis larger than the first length, the TFET device having an effective channel length that is an average of the first and second lengths. The channel region includes a channel material with a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, the first effective mass being greater than the second effective mass.

An oxide semiconductor film contains In, Ga, and Sn at respective atomic ratios satisfying formulae (1) to (3): 0.01Ga/(In+Ga+Sn)0.30 . . . (1); 0.01Sn/(In+Ga+Sn)0.40 . . . (2); and 0.55In/(In+Ga+Sn)0.98 . . . (3), and Al at an atomic ratio satisfying a formula (4): 0.05Al/(In+Ga+Sn+Al)0.30 . . . (4).

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

The magnetoresistance effect element includes a semiconductor layer, a first ferromagnetic layer and a second ferromagnetic layer. The semiconductor layer has a first region, a second region, and a third region. The first ferromagnetic layer is provided on the first region, the second ferromagnetic layer is provided on the second region, and the third region is sandwiched between the first region and the second region in the first direction. The third region has n-type conductivity, and crystal orientations of the semiconductor material in the first direction are substantially the same in the first region, the second region, and the third region. An interatomic distance of the third region in an upper surface neighboring region including the upper surface is larger than an interatomic distance of the first region in the upper surface neighboring region.

The disclosed integrated circuit for offset cross field effect transistors can include a first transistor include a first channel oriented in a first direction; an oxide layer adjacent to the first transistor; and a second transistor adjacent to the oxide layer. The second transistor can include a second channel that is oriented in a direction orthogonal to the first direction, and the first channel and the second channel can be laterally offset such that the second channel does not cross over the first channel. Various other apparatuses, systems, and methods are also disclosed.

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first stacked structure, a second stacked structure, an isolation layer and a gate. The first stacked structure is disposed on a substrate, and includes a first GaN channel layer disposed on the substrate and having an N crystal phase and a first barrier layer disposed on the first GaN channel layer. The second stacked structure is disposed on the substrate, and includes a second GaN channel layer disposed on the substrate and having a Ga crystal phase and a second barrier layer disposed on the second GaN channel layer. The isolation layer is disposed between the first stacked structure and the second stacked structure. The gate is disposed on the first stacked structure, the isolation layer and the second stacked structure.