A high electron mobility transistor (HEMT) device and a method of forming the same are provided. The method includes forming a first III-V compound layer over a substrate. A second III-V compound layer is formed over the first III-V compound layer. The second III-V compound layer has a greater band gap than the first III-V compound layer. A third III-V compound layer is formed over the second III-V compound layer. The third III-V compound layer and the first III-V compound layer comprise a same III-V compound. A passivation layer is formed along a topmost surface and sidewalls of the third III-V compound layer. A fourth III-V compound layer is formed over the second III-V compound layer. The fourth III-V compound layer has a greater band gap than the first III-V compound layer.

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode, a first electrode, a first via and a second via. The substrate has a first surface and a second surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap exceeding that of the first nitride semiconductor layer. The gate electrode and the first electrode are disposed on the second nitride semiconductor layer. The first via extends from the second surface and is electrically connected to the first electrode. The second via extends from the second surface. The depth of the first via is different from the depth of the second via.

The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, and a carbonitride semiconductor layer. The first nitride semiconductor layer is over the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The carbonitride semiconductor layer is between the substrate and the first nitride semiconductor layer.

A substrate electric potential stabilization circuit is configured to be connected to a bidirectional switch element including a first main electrode, a second main electrode, and a backside electrode. The stabilization circuit includes a first switch connected to the first main electrode and the backside electrode in series between the first main electrode and the backside electrode, a second switch connected to the second main electrode and the backside electrode in series between the second main electrode and the backside electrode, and a through-current prevention circuit configured to prevent the first switch and the second switch from being turned on simultaneously. The substrate electric potential stabilization circuit prevents a through-current flowing in this circuit.

The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separate from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, where the field plate extends from a proximal region positioned between the source region and the pedestal, towards the drain region, where at least a portion of the field plate overlaps at least a portion of the pedestal.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.

The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics.

Embodiments of the present application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a first doped nitride semiconductor layer disposed on the semiconductor layer, and a second doped nitride semiconductor layer disposed on the first doped nitride semiconductor layer. The semiconductor device further includes an undoped nitride semiconductor layer between the semiconductor layer and the first doped nitride semiconductor layer. The undoped nitride semiconductor layer has a first surface in contact with the semiconductor layer and a second surface in contact with the first doped nitride semiconductor layer.